Semiconductor devices having staggered air gaps
A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.
1. A semiconductor device comprising:
a substrate;
an interlayer dielectric layer on the substrate;
first, second and third conductive lines that are disposed in series in the interlayer dielectric layer; and
an air gap provided in a space between the first conductive line and the second conductive line.
2. The semiconductor device of claim 1 , wherein the interlayer dielectric layer completely fills a space between the second conductive line and the third conductive line.
3. The semiconductor device of claim 2 , wherein no air gap is provided in a space between the second conductive line and the third conductive line.
4. The semiconductor device of claim 3 , further comprising:
a mask pattern fully overlapping the third conductive line and partially overlapping the second conductive line.
5. The semiconductor device of claim 1 , wherein a bottom of the air gap is higher than a bottom of the first conductive line.
6. A semiconductor device comprising:
a substrate;
an interlayer dielectric layer on the substrate;
first, second, third and fourth lower conductive lines that are disposed in series in the interlayer dielectric layer;
an upper conductive line on the third lower conductive line;
a conductive plug extending from the upper conductive line to the third lower conductive line; and
an air gap provided in a space between the first lower conductive line and the second lower conductive line,
wherein the interlayer dielectric layer completely fills spaces between the second lower conductive line and the third lower conductive line and between the third lower conductive line and the fourth lower conductive line.
7. The semiconductor device of claim 6 , wherein no air gap is provided in spaces between the second lower conductive line and the third lower conductive line and between the third lower conductive line and the fourth lower conductive line.
8. The semiconductor device of claim 6 , wherein a bottom of the air gap is higher than a bottom of the first lower conductive line.
9. A semiconductor device comprising:
a substrate including a first region and a second region spaced apart from each other in a first direction;
lower conductive patterns disposed on the substrate and including first lower conductive patterns on the first region and second lower conductive patterns on the second region;
a first interlayer dielectric layer disposed between the first lower conductive patterns
a lower air gap provided in a space between the second lower conductive patterns;
a middle conductive pattern disposed on the lower conductive pattern in the second region;
upper conductive patterns including first upper conductive patterns disposed on the first lower conductive patterns and second upper conductive patterns disposed on the second lower conductive patterns; and
an upper air gap provided in a space between the second upper conductive patterns,
wherein the first interlayer dielectric layer completely fills a space between the first lower conductive patterns.
10. The semiconductor device of claim 9 , wherein a bottom of the lower air gap is higher than bottoms of the second lower conductive patterns.
11. The semiconductor device of claim 9 , wherein a bottom of the upper air gap is higher than bottoms of the second upper conductive patterns.