Mechanisms for forming package structure

Inventor: Hsien-Wei Chen (Hsinchu, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

H01L24/17 H01L23/49811 H01L24/11 H01L24/14 H01L24/16 H01L24/81 H01L25/0657 H01L25/50 H01L24/05 H01L24/13 H01L2224/0401 H01L2224/05073 H01L2224/05166 H01L2224/05181 H01L2224/05187 H01L2224/05647 H01L2224/11005 H01L2224/1132 H01L2224/11334 H01L2224/11849 H01L2224/131 H01L2224/1403 H01L2224/14051 H01L2224/14131 H01L2224/14134 H01L2224/14164 H01L2224/14177 H01L2224/14179 H01L2224/16058 H01L2224/16225 H01L2224/16227 H01L2224/1703 H01L2224/1713 H01L2224/17051 H01L2224/17135 H01L2224/81193 H01L2224/81815 H01L2225/06513 H01L2225/06517 H01L2924/1305 H01L2924/13091 H01L2924/351 H01L2924/3512 H01L2924/381

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Quick Facts

Patent No.: US 10,141,280
App. No.: 14/614,103
Granted: Nov 27, 2018
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Structures and formation methods of a package structure are provided. The package structure includes a semiconductor die and a substrate bonded to the semiconductor die through a first bonding structure and a second bonding structure therebetween. The first bonding structure and the second bonding structure are next to each other and the second bonding structure is wider than the first bonding structure. The first bonding structure has a first under bump metallurgy (UBM) structure and a first solder bump thereon, and the second bonding structure has a second UBM structure and a second solder bump thereon. The second UBM structure has a maximum width larger than that of the first UBM structure, and the second solder bump has a maximum width larger than that of the first solder bump.

Claims (69)

1. A package structure, comprising:

a semiconductor die; and

a substrate bonded to the semiconductor die through a first bonding structure and a second bonding structure therebetween, wherein:

the first bonding structure and the second bonding structure are next to each other,

the second bonding structure is wider than the first bonding structure,

the first bonding structure has a first under bump metallurgy (UBM) structure and a first solder bump,

the first UBM structure is between the first solder bump and the semiconductor die,

the first solder bump has a first end and a second end opposite to the first end,

the second end is in direct contact with the first UBM structure,

the second end is wider than the first end,

the second bonding structure has a second UBM structure and a second solder bump,

the second solder bump has a third end and a fourth end opposite to the third end,

the fourth end is in direct contact with the second UBM structure,

the third end of the second solder bump is as wide as the first end of the first solder bump,

the second UBM structure has a continuous linear portion extending across an entirety of the fourth end of the second solder bump,

the second UBM structure has a sidewall portion surrounding the continuous linear portion and extending along a side surface of the second solder bump,

the third end of the second solder bump and the first end of the first solder bump are substantially positioned at a plane that is parallel to a main surface of the substrate,

the second UBM structure is between the second solder bump and the semiconductor die, and

the second UBM structure has a maximum width larger than that of the first UBM structure, and the second solder bump has a maximum width larger than that of the first solder bump.

2. The package structure as claimed in claim 1 , wherein the second solder bump has a volume larger than that of the first solder bump.

3. The package structure as claimed in claim 1 , wherein the second solder bump has a height substantially equal to that of the first solder bump.

4. The package structure as claimed in claim 1 , wherein the second solder bump is formed over a high stress region of the semiconductor die.

5. The package structure as claimed in claim 4 , wherein the high stress region is a corner region of the semiconductor die.

6. The package structure as claimed in claim 1 , wherein the main surface of the substrate is substantially parallel to a surface of the semiconductor die.

7. The package structure as claimed in claim 1 , wherein each of the first solder bump and the second solder bump has a sidewall that curves outwards, a widest portion of the second solder bump is laterally aligned with a widest portion of the first solder bump, and the widest portion of the first solder bump is between the first end and the second end of the first solder bump.

8. The package structure as claimed in claim 1 , wherein the maximum width of the first solder bump is at a height of the first solder bump, and a ratio of the height to a total height of the first solder bump is in a range from about 0.4 to about 0.6.

9. The package structure as claimed in claim 1 , wherein the maximum width of the second solder bump is at a height of the second solder bump, and a ratio of the height to a total height of the second solder bump is in a range from about 0.2 to about 0.5.

10. The package structure as claimed in claim 1 , wherein the first solder bump is wider than the first UBM structure, and the second solder bump is wider than the second UBM structure.

11. A package structure, comprising:

a semiconductor die; and

a substrate bonded to the semiconductor die through a first bonding structure and a second bonding structure therebetween, wherein:

the second bonding structure is wider than the first bonding structure, the first bonding structure has a first under bump metallurgy (UBM) structure and a first solder bump,