Gate structure, semiconductor device and the method of forming semiconductor device
A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.
1. A gate structure comprising:
a gate stack comprising:
a doped work function metal (WFM) stack; and
a metal gate electrode overlying the doped WFM stack;
a doped oxide layer in physical contact with a first portion of a sidewall of the gate stack, wherein a surface of the doped oxide layer that extends away from the gate stack and is facing away from a semiconductor substrate is planar; and
a doped spacer over and contacting the doped oxide layer, wherein the doped spacer is in physical contact with a second portion of the sidewall of the gate stack, wherein the doped WFM stack has a dopant concentration lower than a dopant concentration of the doped spacer.
2. The gate structure of claim 1 , wherein the doped WFM stack is doped with boron (B) or arsenic (As).
3. The gate structure of claim 1 , wherein the doped WFM stack comprises a doped TiSiN layer and a doped TiN layer overlying the doped TiSiN layer.
4. The gate structure of claim 3 , wherein the gate stack comprises a doped gate oxide layer underlying the doped TiSiN layer, and the doped gate oxide layer and the doped TiSiN layer are amorphous.
5. The gate structure of claim 1 , wherein the doped spacer is silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbon oxynitride (SiCON), silicon oxyfluoride (SiOF), or a combination thereof.
6. The gate structure of claim 1 , wherein the metal gate electrode is Cu, Al, Ni, Co, Nb, Ta, TaN, TaC, W, WN, WC, or a combination thereof.
7. A semiconductor device comprising:
a substrate with a source region and a drain region;
a gate stack overlying the substrate between the source region and the drain region, comprising:
a doped gate oxide layer;
a doped work function metal (WFM) stack overlying the doped gate oxide layer; and
a metal gate electrode overlying the doped WFM stack;
a doped oxide layer overlying a surface of the substrate, the doped oxide layer physically contacting a sidewall of the doped gate oxide layer, the doped oxide layer having a constant thickness as the doped oxide layer extends away from the gate stack; and
a doped spacer overlying the doped oxide layer and physically contacting a sidewall of the gate stack, wherein the doped WFM stack has a dopant concentration lower than a dopant concentration of the doped spacer.
8. The semiconductor device of claim 7 , wherein the doped WFM stack, the doped spacer, and the doped oxide layer are boron-doped.
9. The semiconductor device of claim 7 , wherein the doped WFM stack, the doped spacer, and the doped oxide layer are arsenic-doped.
10. The semiconductor device of claim 7 , wherein the substrate is a raised fin structure crossed over by the gate stack.
11. The semiconductor device of claim 7 , wherein the doped oxide layer is aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), hafnium oxide (HfO 2 ), silicon dioxide (SiO 2 ), zirconium oxide (ZrO 2 ), or a combination thereof.
12. The semiconductor device of claim 7 , wherein the doped spacer is on only the sidewall of the gate stack and a portion of the doped oxide layer adjacent to the sidewall of the gate stack.
13. The semiconductor device of claim 7 , wherein the doped WFM stack is doped with boron (B) or arsenic (As).
14. The semiconductor device of claim 7 , wherein the doped WFM stack comprises a doped TiSiN layer and a doped TiN layer overlying the doped TiSiN layer.
15. A gate structure comprising:
a gate stack comprising:
a doped work function metal (WFM) layer; and
a metal gate electrode overlying the doped WFM layer;
a doped oxide layer disposed on a portion of a sidewall of the gate stack, the doped oxide layer contacting a sidewall of the doped WFM layer; and
a spacer with a dopant concentration, the spacer disposed on the doped oxide layer and a remaining portion of the sidewall of the gate stack, wherein the doped WFM layer has a dopant concentration lower than a dopant concentration of the spacer, wherein an interface between the spacer and the doped oxide layer extends away from the gate stack in a direction parallel with a semiconductor substrate.
16. The gate structure of claim 15 , wherein the doped oxide layer and the doped WFM layer have the same dopant.
17. The gate structure of claim 15 , wherein the spacer blankets the doped oxide layer.
18. The gate structure of claim 1 , wherein a doped portion of the doped spacer contacts a doped portion of the doped oxide layer.
19. The semiconductor device of claim 1 , wherein the gate stack is in contact with multiple sides of a semiconductor fin.
20. The semiconductor device of claim 15 , wherein the gate stack is in contact with multiple sides of a semiconductor fin.