Increasing the resolution of on-chip measurement circuits

1. A method for increasing a resolution of an on-chip measurement circuit comprising a first circuit and a circuit delay chain comprising a plurality of stages, the method comprising:

propagating, by the first circuit of the on-chip measurement circuit, a first signal through the circuit delay chain of the on-chip measurement circuit to generate a first output;

propagating, by the first circuit of the on-chip measurement circuit, a second signal through the circuit delay chain of the on-chip measurement circuit to generate a second output, wherein the second signal includes a delay; and

reconciling the first output and the second output to determine the resolution of the on-chip measurement circuit by a comparison of the first output and the second output at each stage of the plurality of stages within the on-chip measurement circuit to identify at each stage whether an original transition or a delay transition of the first and second signals occurred,

wherein the resolution of the on-chip measurement circuit increases in correspondence with the delay.

2. The method of claim 1 , wherein the first circuit comprises a programmable circuit of the on-chip measurement circuit coupled to the circuit delay chain of the on-chip measurement circuit.

3. The method of claim 1 , wherein the first circuit comprises one of a plurality of parallel circuits of the on-chip measurement circuit, each of parallel circuit providing a different value for the delay.

4. The method of claim 1 , further comprising:

iteratively swapping through a plurality of signals to determine the resolution of the on-chip measurement circuit.

5. The method of claim 4 , wherein the plurality of signals comprises at least the first and the second signals.

6. The method of claim 1 , wherein the delay of the second signal is less than a delay of each stage of the on-chip measurement circuit.

7. The method of claim 1 , wherein the delay of the second signal is a programmable delay at the start of a circuit delay line of the on-chip measurement circuit.

8. A system for increasing a resolution of an on-chip measurement circuit, the system comprising the on-chip measurement circuit, the on-chip measurement circuit comprising a first circuit and a circuit delay chain comprising a plurality of stages, the system being configured to:

propagate, by the first circuit, a first signal through the on-chip measurement circuit to generate a first output;

propagate, by the first circuit, a second signal through the on-chip measurement circuit to generate a second output, wherein the second signal includes a delay; and

reconcile the first output and the second output to determine the resolution of the on-chip measurement circuit by a comparison of the first output and the second output at each stage of the plurality of stages within the on-chip measurement circuit to identify at each stage whether an original transition or a delay transition of the first and second signals occurred,

wherein the resolution of the on-chip measurement circuit increases in correspondence with the delay.

9. The system of claim 8 , wherein the first circuit comprises a programmable circuit of the on-chip measurement circuit coupled to a circuit delay chain of the on-chip measurement circuit.

10. The system of claim 8 , wherein the first circuit comprises one of a plurality of parallel circuits of the on-chip measurement circuit, each of parallel circuit providing a different value for the delay.

11. The system of claim 8 , the system configured to:

iteratively swap through a plurality of signals to determine the resolution of the on-chip measurement circuit.

12. The system of claim 11 , wherein the plurality of signals comprises at least the first and the second signals.

13. The system of claim 8 , wherein the delay of the second signal is less than a delay of each stage of the on-chip measurement circuit.

14. The system of claim 8 , wherein the delay of the second signal is a programmable delay at the start of a circuit delay line of the on-chip measurement circuit.

15. An on-chip measurement circuit comprising:

a circuit delay chain comprising a plurality of stages, the circuit delay chain being configured to receive and propagate a plurality of signals to execute a measurement; and

a programmable device configured to provide the plurality of signals to the circuit delay chain,

wherein the programmable device implements a delay in at least one of the plurality of signals to increase a resolution of the measurement of the circuit delay chain,

wherein the on-chip measurement circuit reconciles the first output and the second output to determine the resolution of the on-chip measurement circuit by a comparison of the first output and the second output at each stage of the plurality of stages within the on-chip measurement circuit to identify at each stage whether an original transition or a delay transition of the first and second signals occurred,

wherein the first and second outputs respectively correspond to first and second signals,

wherein the resolution of the on-chip measurement circuit increases in correspondence with the delay.

16. The on-chip measurement circuit of claim 15 , wherein the on-chip measurement circuit is configured to iteratively swap through the plurality of signals to determine the resolution of the on-chip measurement circuit.