High performance interconnect physical layer
A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.
1. A processor device comprising:
a transmitter port comprising physical layer logic to:
send a request to enter a partial width state to a remote agent, wherein the request is sent over a link during a control link state comprising a timed state during which link layer flits are held off while physical layer information is to be communicated to the remote agent, the link comprises a plurality of lanes, a subset of the plurality of lanes of the link are to be used during the partial width state, and lanes in the plurality of lanes not included in the subset are to be idle lanes during the partial width state;
turn off the idle lanes in a staggered manner; and
send a link layer flit over the subset of lanes during the partial width state; and
wherein the transmitter further comprises link layer logic to generate the link layer flit.
2. The processor device of claim 1 , wherein the transmitter port is to transmit on each of the plurality of lanes.
3. The processor device of claim 1 , wherein the plurality of lanes comprises 20 lanes and the subset of lanes comprise 8 lanes.
4. The processor device of claim 1 , further comprising a receiver port to receive data on the plurality of lanes of the link.
5. The processor device of claim 4 , wherein the receiver port is to receive data on only the subset of lanes during the partial width state.
6. The processor device of claim 1 , wherein the control link state is to periodically interrupt a link transmitting state.
7. The processor device of claim 1 , wherein the request to enter the partial width state comprises a supersequence, and the supersequence comprises a repeating pattern.
8. The processor device of claim 7 , wherein the repeating pattern comprises an electrical ordered set (EOS) and a plurality of training sequences.
9. The processor device of claim 8 , wherein the EOS comprises an electrical idle exit ordered set (EIEOS).
10. The processor device of claim 8 , wherein the plurality of training sequences comprises a predefined number of training sequences to be sent in series within the repeating pattern.
11. The processor device of claim 10 , wherein the predefined number comprises six training sequences.
12. The processor device of claim 8 , wherein the training sequences comprise fast training sequences.
13. A method comprising:
sending the link layer flits during a transmitting link state;
sending a request to enter a partial width state to a remote agent, wherein the request is sent over a link during a control link state comprising a timed state during which link layer flits are held off while physical layer information is to be communicated to the remote agent, the control link state is to be entered periodically to interrupt the transmitting link state, the link comprises a plurality of lanes, a subset of the plurality of lanes of the link are to be used during the partial width state, and lanes in the plurality of lanes not included in the subset are to be idle lanes during the partial width state;
turning off the idle lanes in a staggered manner; and
sending a link layer flit over the subset of lanes during the partial width state.
14. The method of claim 13 , wherein all of the plurality of lanes are to be used to send the link layer flits during the transmitting link state.
15. An apparatus comprising:
a controller to interface between at least a first processor to recognize a first instruction set and second processor to recognize a second instruction set that is different from the first instruction set, the controller comprising protocol layer logic, link layer logic, and physical layer logic, wherein the physical layer logic is to:
send a request to enter a partial width state to another device, wherein the request is sent over a link during a periodic control window in which link layer flits are held off while physical layer control information is to be communicated to the first device, the link comprises a plurality of lanes, a subset of the plurality of lanes of the link are to be used during the partial width state, lanes in the plurality of lanes outside the subset are to be transitioned to an idle state during the partial width state, the request to enter the partial width state comprises a supersequence, and the supersequence comprises a repeating pattern;
transition the lanes outside the plurality of lanes to the idle state in a staggered manner; and
send a link layer flit to the first device over the subset of lanes during the partial width state.
16. The apparatus of claim 15 , wherein the repeating pattern comprises an electrical idle exit ordered set (EIEOS) and a plurality of training sequences.
17. The apparatus of claim 16 , wherein the plurality of training sequences comprise a predefined number of fast training sequences to be sent in the repeating pattern.
18. A system comprising:
a first device;
a second device to connect to the first device via a link, wherein the second device comprises physical layer logic to:
send a request to enter a partial width state to the first device, wherein the request is sent over the link during a control link state comprising a timed state during which link layer flits are held off while physical layer information is to be communicated to the first device, the link comprises a plurality of lanes, a subset of the plurality of lanes of the link are to be used during the partial width state, and lanes in the plurality of lanes outside the subset are to be transitioned to an idle state during the partial width state, wherein the request to enter the partial width state comprises a supersequence, and the supersequence comprises a repeating pattern;
stagger transitions of the lanes outside the plurality of lanes to the idle state; and
send a link layer flit to the first device over the subset of lanes during the partial width state.
19. The system of claim 18 , wherein one or both of the first and second devices comprises a processor node.
20. The system of claim 18 , wherein one or both of the first and second devices comprises an accelerator.
21. The system of claim 18 , wherein one or both of the first and second devices comprises a node controller.
22. The system of claim 18 , wherein the first device comprises physical layer logic to:
receive the request to enter a partial width state from the second device;
participate in staggering transitions of the lanes outside the plurality of lanes to the idle state; and
receive the link layer flit from the second device over the subset of lanes during the partial width state.