Techniques for trench isolation using flowable dielectric materials
Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids. After curing, the resultant dielectric layer can undergo wet chemical, thermal, and/or plasma treatment, for instance, to modify at least one of its dielectric properties, density, and/or etch rate.
1. An integrated circuit comprising:
a semiconductive substrate having a plurality of semiconductive fins extending from an upper surface thereof and a trench between a given pair of neighboring semiconductive fins, wherein the trench has a width between fins that is less than or equal to 20 nm and a height-to-width aspect ratio in the range of 20:1 to 45:1;
a dielectric layer over the semiconductive substrate, wherein the dielectric layer partially fills the trench, the dielectric layer extending from the upper surface of the semiconductive substrate to a point below an active portion of each of the semiconductive fins, and wherein the dielectric layer comprises a carbide or a nitride, or both a carbide and a nitride; and
a transistor device on the active portion of at least one of the fins.
2. The integrated circuit of claim 1 wherein the trench has a height-to-width aspect ratio in the range of 25:1 to 45:1.
3. The integrated circuit of claim 1 wherein the trench has a height-to-width aspect ratio in the range of 30:1 to 45:1.
4. The integrated circuit of claim 1 wherein the dielectric layer is completely free of seam and void defects.
5. The integrated circuit of claim 1 wherein the trench has sidewalls substantially perpendicular to the upper surface of the semiconductive substrate.
6. The integrated circuit of claim 1 wherein the dielectric layer has a lower dielectric constant (κ-value) relative to silicon dioxide.
7. A method of forming an integrated circuit, the method comprising:
providing a semiconductive substrate having a plurality of semiconductive fins extending from an upper surface thereof and a trench formed between each pair of neighboring semiconductive fins, wherein the trench has a width between fins that is less than or equal to 20 nm and a height-to-width aspect ratio in the range of 20:1 to 45:1;
depositing a flowable dielectric material over the semiconductive substrate, wherein the flowable dielectric material partially fills the trench;
curing the flowable dielectric material to provide a dielectric layer, the dielectric layer extending from the upper surface of the semiconductive substrate to a point below an active portion of each of the semiconductive fins;
treating the dielectric layer to modify at least one of its dielectric properties, density, and etch rate, wherein treating the dielectric layer comprises applying a thermal treatment, and wherein the dielectric layer comprises a carbide or a nitride, or both a carbide and a nitride; and
forming a transistor device on the active portion of at least one of the fins.
8. The method of claim 7 wherein depositing the flowable dielectric material over the semiconductive substrate comprises using a flowable chemical vapor deposition (FCVD) process.
9. The method of claim 8 wherein the FCVD process utilizes remote plasma-enhanced CVD (RPECVD).
10. The method of claim 7 wherein the flowable dielectric material comprises at least one of a silazane (SiH 2 NH) n -based polymer and Trisilylamine (N(SiH 3 ) 3 ).
11. The method of claim 7 wherein curing the flowable dielectric is performed at a temperature in the range of about 120-180 ° C.
12. The method of claim 7 wherein curing the flowable dielectric comprises exposing it to at least one of ozone (O 3 ) and oxygen (O 2 ).
13. The method of claim 7 wherein treating the dielectric layer comprises applying a wet chemical treatment that utilizes at least one of ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ), hot de-ionized water (HDIW), and de-ionized water (DIW) at a temperature in a range of from 40° C. to 80° C.
14. The method of claim 7 wherein treating the dielectric layer comprises at least one of furnace annealing, rapid thermal annealing, flash annealing, plasma annealing, and ultraviolet (UV) light-based oxidation.
15. The method of claim 7 wherein treating the dielectric layer comprises a furnace-based vertical directional solidification (VDS) process in which the dielectric layer is subjected to an environment of about 90% steam or greater for a first period of time at a first temperature in the range of about 180-240 ° C. and for a second period of time at a second temperature in the range of about 450-525 ° C.
16. The method of claim 7 wherein treating the dielectric layer comprises each of a wet chemical treatment, a furnace treatment, and a plasma anneal.
17. The method of claim 16 , further comprising:
planarizing the dielectric layer; and
etching the dielectric layer to recess it to a point below the active portion of at least one of the semiconductive fins.