IP Library › Granted Patent US 10,147,646
Granted Patent B2
US 10,147,646 · App. 15/811,733 · Granted Dec 4, 2018

Manufacturing process of element chip

Inventors: Hidehiko Karasaki (Osaka, JP); Hidefumi Saeki (Osaka, JP); Atsushi Harikai (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H01L21/78H01L21/2686
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,147,646
App. No.
15/811,733
Granted
Dec 4, 2018
Kind
B2
Abstract

A manufacturing process of an element chip comprises a preparation step for preparing a substrate, the substrate including first and second streets crossing each other to define a plurality of element regions. Also, it comprises a first shallow-groove formation step for radiating a laser beam along the first streets to form a plurality of first shallow grooves being shallower than a thickness of the substrate, a second shallow-groove formation step for radiating the laser beam along the second streets to form a plurality of second shallow grooves being shallower than a thickness of the substrate, a first groove formation step for radiating the laser beam along the first shallow grooves to form a plurality of first grooves, and a plasma dicing step for etching the substrate along the first grooves and the second shallow grooves by a plasma exposure to dice the substrate into a plurality of element chips.

Claims (33)

1. A manufacturing process of an element chip, comprising:

a preparation step for preparing a substrate having first and second sides, the substrate including a first layer of a semiconductor layer, a second layer having an outermost protective layer, and a plurality of element regions, and a plurality of first and second streets crossing each other to define each of the element regions;

a laser scribing step for radiating a laser beam to the first side along the first and second streets to form a plurality of first and second grooves along the streets, the first and second grooves being shallower than a thickness of the substrate;

after the laser scribing step, a plasma dicing step for etching the rest of the substrate remaining in a direction of a depth along the first and second grooves through the substrate by a plasma exposure to the grooves to dice the substrate into a plurality of element chips each having the element region;

wherein the laser scribing step includes,

a first shallow-groove formation step for radiating the laser beam N 1 times (N 1 ≥1) onto the first streets to form first shallow grooves each shallower than the first groove;

after the first shallow-groove formation step, a second shallow-groove formation step for radiating the laser beam M 1 times (M 1 ≥1) onto the second streets to form second shallow grooves each shallower than the second groove;

after the second shallow-groove formation step, a second groove formation step for radiating the laser beam M 2 times (M 2 ≥1) onto the second shallow grooves until the second grooves are formed; and

after the first shallow-groove formation step, and after the second shallow-groove formation step or the second groove formation step, a first groove formation step for radiating the laser beam N 2 times (N 2 ≥1) onto the first shallow grooves until the first grooves are formed.

2. The manufacturing process according to claim 1 , wherein the first shallow grooves have a depth of 50% or more of that of the first grooves.

3. The manufacturing process according to claim 1 , wherein N 2 equals to one.

4. The manufacturing process according to claim 1 , wherein M 2 equals to one.

5. The manufacturing process according to claim 1 , wherein N 1 equals to two or more and the first shallow-groove formation steps are made in series, and wherein the sum of M 1 and M 2 is two or more and the second shallow-groove formation step and the second groove formation step are made in series.

6. A manufacturing process of an element chip, comprising:

a preparation step for preparing a substrate having first and second sides, the substrate including first and second streets crossing each other to define a plurality of element regions on the first side;

a first shallow-groove formation step for radiating a laser beam along the first streets to form a plurality of first shallow grooves, the first shallow grooves being shallower than a thickness of the substrate;

a second shallow-groove formation step for radiating the laser beam along the second streets to form a plurality of second shallow grooves, the second shallow grooves being shallower than a thickness of the substrate;

a first groove formation step for radiating the laser beam along the first shallow grooves to form a plurality of first grooves; and

a plasma dicing step for etching the substrate along the first grooves and the second shallow grooves by a plasma exposure to dice the substrate into a plurality of element chips each having the element region.

7. The manufacturing process according to claim 6 , further comprising a second groove formation step for radiating the laser beam along the second shallow grooves to form a plurality of second grooves.

8. The manufacturing process according to claim 7 , the second shallow-groove formation step and the second groove formation step are made in series.

9. The manufacturing process according to claim 6 , wherein at least either one of the first shallow-groove formation step and the second shallow-groove formation step is repeatedly made multiple times.

10. The manufacturing process according to claim 6 , wherein the first shallow grooves have a depth of 50% or more of that of the first grooves.

11. A manufacturing process of an element chip, comprising:

a preparation step for preparing a substrate having first and second sides, the substrate including first and second streets crossing each other to define a plurality of element regions on the first side;

a first shallow-groove formation step for radiating a laser beam along the first streets to form a plurality of first shallow grooves, the first shallow grooves being shallower than a thickness of the substrate;

a second shallow-groove formation step for radiating the laser beam along the second streets to form a plurality of second shallow grooves, the second shallow grooves being shallower than a thickness of the substrate;

a second groove formation step for radiating the laser beam along the second shallow grooves to form a plurality of second grooves;

a first groove formation step for radiating the laser beam along the first shallow grooves to form a plurality of first grooves; and

a plasma dicing step for etching the substrate along the first grooves and the second grooves by a plasma exposure to dice the substrate into a plurality of element chips each having the element region.

12. The manufacturing process according to claim 11 , wherein at least either one of the first shallow-groove formation step and the second shallow-groove formation step is repeatedly made multiple times.

13. The manufacturing process according to claim 11 , the second shallow-groove formation step and the second groove formation step are made in series.

14. The manufacturing process according to claim 11 , wherein the first shallow grooves have a depth of 50% or more of that of the first grooves.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2018
From: KARASAKI, HIDEHIKO; SAEKI, HIDEFUMI; HARIKAI, ATSUSHI
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 044779/0264 →
Priority Claims (1)
JP 2016-243325 · Dec 15, 2016 · national
Continuity (1)
Related Publication 20180174908A1 · Jun 21, 2018
Cited By (1)
US 12,230,484