IP Library Granted Patent US 10,148,293
Granted Patent B2
US 10,148,293 · App. 15/072,009 · Granted Dec 4, 2018

Incremental LLR generation for flash memories

Inventors: Fan Zhang (Fremont, CA); David J. Pignatelli (Saratoga, CA); June Lee (Sunnyvale, CA)
Assignee: SK Hynix Inc.
H03M13/45G06F11/1004G06F11/1012H03M13/3723H03M13/6325H03M13/1111H03M13/152H03M13/1515H03M13/251H03M13/256H03M13/2957H03M13/2963
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Quick Facts
Patent No.
US 10,148,293
App. No.
15/072,009
Granted
Dec 4, 2018
Kind
B2
Abstract

Methods for decoding information stored on a memory may include performing a hard read at an initial threshold and determining a first distribution percentage, performing a hard read at a subsequent threshold and determining a second distribution percentage, generating a log-likelihood ratio (LLR) based on the hard reads performed at the initial and subsequent thresholds, and based on the first and second distribution percentages, and soft decoding the information based on the generated LLR.

Claims (47)

1. A method for decoding information stored on a memory, comprising:

performing a first hard read of the information by using a first threshold and determining a first distribution percentage, which is a percentage of one of two symbols in the first hard read;

performing a second hard read of the information by using a second threshold and determining a second distribution percentage, which is a percentage of the one symbol in the second hard read;

generating a log-likelihood ratio (LLR) based on the first and second hard reads performed by using the first and second thresholds respectively, and based on the first and second distribution percentages, including estimating a voltage level corresponding to about 50% of the one symbol read in the first and second hard reads; and

performing a first soft decoding of the information based on the generated LLR.

2. The method of claim 1 , further comprising, if the first soft decoding fails:

performing a third hard read of the information by using third threshold;

determining a third distribution percentage;

generating an additional LLR based on the third hard read and at least one of the first and second hard reads, and based on the third distribution percentage and at least one of the first and second distribution percentages; and

performing a second soft decoding of the information based on the generated additional LLR.

3. The method of claim 1 , wherein the one symbol is 1.

4. The method of claim 1 , further comprising forming an interval using the first threshold and the second threshold.

5. The method of claim 4 , wherein the generating of the LLR includes:

finding an LLR value for a middle point of the interval; and

assigning the found LLR value to memory cells in the interval, wherein the memory cells have hard reads of 0 in the first hard read using the first threshold and hard reads of 1 in the second hard read using the second threshold.

6. A system for decoding information stored on a memory, comprising:

a semiconductor memory device;

a controller coupled with the semiconductor memory device and configured to:

perform a first hard read of the information by using a first threshold and determining a first distribution percentage, which is a percentage of one of two symbols in the first hard read;

perform a second hard read of the information by using a second threshold and determining a second distribution percentage, which is a percentage of the one symbol in second hard read; and

generate a log-likelihood ratio (LLR) based on the first and second hard reads performed by using the first and second thresholds respectively, and based on the first and second distribution percentages, including estimating a voltage level corresponding to about 50% of the one symbol read in the first and second hard reads; and

a decoder configured to perform a first soft decoding of the information based on the generated LLR.

7. The system of claim 6 , wherein the controller is further configured to, if first soft decoding fails:

perform a third hard read of the information by using a third threshold;

determine a third distribution percentage, and

generate an additional LLR based on the third hard read and at least one of the first and second hard reads, and based on the third distribution percentage and at least one of the first and second distribution percentages.

8. The system of claim 6 , wherein the one symbol is 1.

9. The system of claim 6 , wherein the controller is further configured to form an interval using the first threshold and the second threshold.

10. The system of claim 9 , wherein the controller is further configured to:

find an LLR value for a middle point of the interval; and

assign the found LLR value to memory cells in the interval, wherein the memory cells have hard reads of 0 in the first hard read using the first threshold and hard reads of 1 in the second hard read using the second threshold.

11. A memory device, comprising:

a controller configured to:

perform a first hard read of data by using a first threshold and determine a first distribution percentage, which is a percentage of a certain value in the first hard read;

perform a second hard read of the data by using a second threshold and determine a second distribution percentage, which is percentage of a certain value in the second hard read; and

generate a log-likelihood ratio (LLR) based on the first and second hard reads performed at the first and second thresholds respectively, and based on the first and second distribution percentages, including estimating a voltage level corresponding to about 50% of 1s read in the first and second hard reads.

12. The memory device of claim 11 , further comprising:

a decoder configured to perform a soft decode of the data based on the generated LLR.

13. The memory device of claim 12 , wherein the controller is further configured to, if the soft decoding fails:

perform a third hard read of the data at third threshold;

determine a third distribution percentage; and

generate an additional LLR based on the third hard read and at least one of the first and second hard reads, and based on the third distribution percentage and at least one of the first and second distribution percentages.

14. The memory device of claim 11 , wherein the one symbol is 1.

15. The memory device of claim 11 , wherein the controller is further configured to form an interval using the first threshold and the second threshold.

16. The memory device of claim 15 , wherein the controller is further configured to:

find an LLR value for a middle point of the interval; and

assign the found LLR value to memory cells in the interval, wherein the memory cells have hard reads of 0 in the first hard read using the first threshold and hard reads of 1 in the second hard read using the second threshold.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2017
From: SK HYNIX MEMORY SOLUTIONS INC.
To: SK HYNIX INC.
Reel/Frame 044899/0443 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 6, 2016
From: ZHANG, FAN; PIGNATELLI, DAVID J.; LEE, JUNE
To: SK HYNIX MEMORY SOLUTIONS INC.
Reel/Frame 039089/0719 →
Continuity (2)
Provisional Application 62134369 · Mar 17, 2015
Related Publication 20160277041A1 · Sep 22, 2016