Instruction and logic to provide SIMD secure hashing round slice functionality

1. A processor comprising:

a plurality of SIMD (Single Instruction Multiple Data) registers;

a decode stage to decode a first instruction for a SIMD secure hashing algorithm round slice, the first instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the SIMD secure hashing algorithm round slice, and a rotator set portion of rotate settings; and

one or more execution units, responsive to the decoded first instruction, to:

perform a set of round iterations, of the SIMD secure hashing algorithm round slice, upon the source data operand set, applying the message-plus-constant operand set and the rotator set portion of rotate settings; and

store a result of the first instruction in a SIMD destination register.

2. The processor of claim 1 , wherein the first instruction specifies said SIMD destination register as a destination operand.

3. The processor of claim 1 , wherein for a first round iteration of the set of round iterations, said one or more execution units, responsive to the decoded first instruction:

select a message-plus-constant for the first round iteration from the message-plus-constant operand set,

process a portion of the source data operand set according to the first round iteration,

add the selected message-plus-constant to the processed portion of the source data operand set;

generate an output state as a result of the first round iteration; and

bypass the output state to an input state for a second round iteration of the set of round iterations, wherein the second round iteration is after the first round iteration.

4. The processor of claim 1 , wherein the first instruction specifies said round-slice portion of the SIMD secure hashing algorithm round slice by a first field in an immediate operand.

5. The processor of claim 4 , wherein the first instruction specifies said rotator set portion of rotate settings by a second field in the immediate operand.

6. The processor of claim 4 , wherein said secure hashing algorithm round slice is for an MD5 algorithm.

7. The processor of claim 4 , wherein said secure hashing algorithm round slice is for a SHA-1 algorithm.

8. The processor of claim 4 , wherein said secure hashing algorithm round slice is for a SHA-2 algorithm.

9. A method comprising:

storing in a first portion of a plurality of m data fields of a first vector register, an input state source operand of a hash algorithm;

storing in a second portion of the plurality of m data fields of a second vector register, a message-plus-constant operand set of the hash algorithm;

executing, in a processor, a SIMD (Single Instruction Multiple Data) instruction for a hash-round-slice having a plurality of iterations less than a total number of round iterations of the hash algorithm;

applying the message-plus-constant operand set and a rotator set portion of rotate settings in the plurality of iterations of the hash-round-slice upon the input state source operand; and

for each iteration of the hash-round-slice, storing an output state generated as a result of the iteration, and bypassing the output state to input state for each next iteration of the plurality of iterations.

10. The method of claim 9 , each iteration of the hash-round-slice comprising:

selecting a message-plus-constant of an iteration from the message-plus-constant operand set,

processing a portion of the input state source operand according to a round type specified by the SIMD instruction,

adding the selected message-plus-constant to the processed portion of the input state source operand, and

generating a result of the iteration.

11. The method of claim 10 , wherein the SIMD instruction specifies said round type as one of four MD5 round types.

12. The method of claim 11 , each iteration of the hash-round-slice further comprising:

performing a bitwise rotate, according to a rotation value of a rotate set specified by the SIMD instruction, of a sum from adding the selected message-plus-constant to the processed portion of the input state source operand.

13. The method of claim 10 , wherein the SIMD instruction specifies said round type as one of three SHA-1 round types.

14. The method of claim 13 , each iteration of the hash-round-slice comprising:

performing a bitwise rotate, according to a first rotation value of a rotate set specified by the SIMD instruction, of a first portion of the input state source operand to generate a first rotated value;

performing a bitwise rotate, according to a second rotation value of the rotate set specified by the SIMD instruction, of a second portion of the input state source operand to generate a second rotated value; and

adding the first rotated value to a sum from adding the selected message-plus-constant to the processed portion of the input state source operand.

15. The method of claim 10 , wherein the SIMD instruction specifies said round type as a SHA-2 round type.

16. The method of claim 10 , wherein the SIMD instruction specifies said round type by a first field in an immediate operand.

17. The method of claim 16 wherein the SIMD instruction specifies a rotate set by a second field in the immediate operand.

18. A processing system comprising:

a memory to store a first instruction for a SIMD (Single Instruction Multiple Data) secure hashing algorithm round slice; and

a processor comprising:

an instruction fetch stage to fetch the first instruction;

a decode stage to decode the first instruction, the first instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the SIMD secure hashing algorithm round slice, and a rotator set portion of rotate settings; and

an execution stage, responsive to the decoded first instruction, to:

perform a set of round iterations, of the SIMD secure hashing algorithm round slice, upon the source data operand set, applying the message-plus-constant operand set and the rotator set portion of rotate settings; and

store a result of the first instruction in a SIMD destination register.

19. The processing system of claim 18 , wherein the first instruction specifies said round-slice portion of the SIMD secure hashing algorithm round slice by a field in an immediate operand.

20. The processing system of claim 19 wherein the first instruction specifies said rotator set portion of rotate settings by a field in the immediate operand.

21. A processor comprising:

a plurality of registers;

a decode stage to decode a Single Instruction Multiple Data (SIMD) instruction for a round-slice portion of an MD5 secure hashing algorithm, the SIMD instruction specifying a source data operand set, a message-plus-constant operand set, the round-slice portion of the MD5 secure hashing algorithm through a field in an immediate operand, and a rotator set portion of rotate settings; and

an execution unit, responsive to the decode of the SIMD instruction, to:

perform a set of round iterations, of the round-slice portion of the MD5 secure hashing algorithm, upon the source data operand set, applying the message-plus-constant operand set and the rotator set portion of rotate settings; and

store a result of the SIMD instruction in a destination register of the plurality of registers.

22. A processor comprising:

a plurality of registers;

a decode stage to decode a Single Instruction Multiple Data (SIMD) instruction for a round-slice portion of an SHA-1 secure hashing algorithm, the SIMD instruction specifying a source data operand set, a message-plus-constant operand set, the round-slice portion of the SHA-1 secure hashing algorithm through a field in an immediate operand, and a rotator set portion of rotate settings; and

an execution unit, responsive to the decode of the SIMD instruction, to:

perform a set of round iterations, of the round-slice portion of the SHA-1 secure hashing algorithm, upon the source data operand set, applying the message-plus-constant operand set and the rotator set portion of rotate settings; and

store a result of the SIMD instruction in a destination register of the plurality of registers.