IP Library › Granted Patent US 10,153,233
Granted Patent B1
US 10,153,233 · App. 15/655,596 · Granted Dec 11, 2018

Interconnect structure and fabricating method thereof

Inventors: Chi-Hao Huang (Hsinchu, TW); Chin-Cheng Yang (Hsinchu, TW)
Assignee: MACRONIX International Co., Ltd.
H01L23/5283H01L21/76805H01L21/76831H01L23/5221H01L23/5226
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Quick Facts
Patent No.
US 10,153,233
App. No.
15/655,596
Granted
Dec 11, 2018
Kind
B1
Abstract

An interconnect structure including a first dielectric layer, a first conductive layer, a second conductive layer, a capping layer, and a via is provided. The first dielectric layer has a first trench and a second trench. The first conductive layer is located in the first trench. The second conductive layer is located in the second trench, and a top surface of the second conductive layer is lower than a top surface of the first dielectric layer. The capping layer having a via opening exposing a portion of the first conductive layer covers the first dielectric layer, the first conductive layer, and the second conductive layer. The via located on the first conductive layer and the first dielectric layer located between the first conductive layer and the second conductive layer is filled into the via opening and electrically connected to the first conductive layer.

Claims (13)

1. An interconnect structure, comprising:

a first dielectric layer, having a first trench and a second trench;

a first conductive layer, located in the first trench;

a second conductive layer, located in the second trench, and a top surface of the second conductive layer is lower than a top surface of the first dielectric layer;

a capping layer, covering the first dielectric layer, the first conductive layer, and the second conductive layer, and having a via opening exposing a portion of the first conductive layer; and

a via, located on the first conductive layer and the first dielectric layer between the first conductive layer and the second conductive layer, filled into the via opening, and electrically connected to the first conductive layer,

wherein the via covers the second conductive layer.

2. The interconnect structure as claimed in claim 1 , wherein a top surface of the first conductive layer is lower than a top surface of the first dielectric layer.

3. The interconnect structure as claimed in claim 1 , wherein a minimum distance between the via and the second conductive layer is greater than or equal to a shift threshold D s , and D s =8 nm.

4. The interconnect structure as claimed in claim 3 , wherein the capping layer fills the second trench.

5. The interconnect structure as claimed in claim 4 , wherein a second distance y in a Y direction is provided between the via and the second conductive layer, and y≥D s .

6. The interconnect structure as claimed in claim 1 , further comprising:

a second dielectric layer, covering the capping layer and surrounding the via.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2017
From: HUANG, CHI-HAO; YANG, CHIN-CHENG
To: MACRONIX INTERNATIONAL CO., LTD.
Reel/Frame 043058/0090 →
Cited By (1)
US 12,642,079