Interconnect feature contacted within a recess
An integrated circuit device includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes (i) a first dielectric material, (ii) a recess within the first dielectric material, and (iii) a first interconnect feature within the recess. In an example, a top surface of the first interconnect feature is at least 1 nanometer (nm), or at least 3 nm, or at least 5 nm below a top surface of the first dielectric material. The second interconnect layer includes (i) a second dielectric material, and (ii) a second interconnect feature within the second dielectric material. In an example, the second interconnect feature is at least in part above, and conductively coupled to, the first interconnect feature. In an example, a bottom section of the second interconnect feature is within a top section of the recess.
1 . An integrated circuit device comprising:
a first interconnect layer comprising (i) a first dielectric material, (ii) a recess within the first dielectric material, and (iii) a first interconnect feature within the recess, wherein a top surface of the first interconnect feature is at least 1 nanometer (nm) below a top surface of the first dielectric material;
a second interconnect layer above the first interconnect layer, the second interconnect layer comprising (i) a second dielectric material, and (ii) a second interconnect feature within the second dielectric material, wherein the second interconnect feature is at least in part above, and conductively coupled to, the first interconnect feature, and wherein a bottom section of the second interconnect feature is within a top section of the recess; and
a conformal layer separating at least a section of the first dielectric material from a corresponding section of the second dielectric material;
wherein the second interconnect layer further comprises a third interconnect feature within the second dielectric material, wherein a portion of a bottommost surface of the third interconnect feature is directly on a portion of the conformal layer and is directly above a portion of the first interconnect feature, such that the conformal layer is between the portion of the bottommost surface of the third interconnect feature and the portion of the first interconnect feature.
2 . The integrated circuit device of claim 1 , wherein:
a first section of a bottom surface of the second interconnect feature is above and on the first interconnect feature; and
a second section of the bottom surface of the second interconnect feature is above and on the first dielectric material.
3 . The integrated circuit device of claim 1 ,
wherein the conformal layer is absent between a junction of the first interconnect feature and the second interconnect feature.
4 . The integrated circuit device of claim 3 , wherein:
a section of the second interconnect feature is above a first section of a top surface of the first interconnect feature, and not above a second section of the top surface of the first interconnect feature; and
the conformal layer is above and on the second section of the top surface of the first interconnect feature.
5 . The integrated circuit device of claim 4 , wherein:
the second dielectric material extends at least in part within the recess, above the second section of the top surface of the first interconnect feature; and
the conformal layer separates the second section of the top surface of the first interconnect feature from the second dielectric material extending at least in part within the recess.
6 . The integrated circuit device of claim 3 , wherein:
the second interconnect layer comprises a third interconnect feature within the second dielectric material; and
a section of the third interconnect feature is above the first interconnect feature, the section of the third interconnect feature separated from the first interconnect feature by the conformal layer.
7 . The integrated circuit device of claim 3 , wherein the conformal layer comprises at least one of oxygen or nitrogen.
8 . The integrated circuit device of claim 1 , wherein:
a section of the second dielectric material extends within the recess, such that a bottom surface of the section of the second dielectric material extending within the recess is at a lower level than the top surface of the first dielectric material.
9 . The integrated circuit device of claim 8 , wherein:
the section of the second dielectric material extending within the recess is a first section of the second dielectric material; and
a second section of the second dielectric material outside the recess has another bottom surface that is at a higher level than the top surface of the first dielectric material.
10 . The integrated circuit device of claim 1 , wherein the first interconnect feature comprises a first conductive material, and the second interconnect feature comprises a second conductive material, with a seam or an interface at a junction of the first and second conductive materials.
11 . The integrated circuit device of claim 1 , wherein the top surface of the first interconnect feature is at least 3.5 nm below the top surface of the first dielectric material.
12 . The integrated circuit device of claim 1 , wherein the first interconnect feature is a conductive via, and the second interconnect feature is a conductive line.
13 . An integrated circuit device comprising:
a first dielectric material, and a recess within the first dielectric material;
a first interconnect feature within a bottom portion of the recess, the first interconnect feature not within a top portion of the recess;
a second dielectric material above the first dielectric material;
a second interconnect feature within the second dielectric material; and
a conformal layer separating at least a section of the first dielectric material from a corresponding section of the second dielectric material,
wherein a portion of a bottommost surface of the second interconnect feature is directly on a portion of the conformal layer and is directly above a portion of the first interconnect feature, such that the conformal layer is between the portion of the bottommost surface of the second interconnect feature and the portion of the first interconnect feature.
14 . The integrated circuit device of claim 13 , wherein the bottom portion of the recess, which includes the first interconnect feature, is at most 90% of the recess.
15 . The integrated circuit device of claim 13 , wherein:
a first section of the second dielectric material is within the top portion of the recess;
a second section of the second dielectric material is outside the recess;
a first bottom surface of the first section of the second dielectric material is at a lower level than a top surface of the first dielectric material; and
a second bottom surface of the second section of the second dielectric material is at a higher level than the top surface of the first dielectric material.
16 . The integrated circuit device of claim 13 , wherein the first interconnect feature comprises a first conductive material, and the second interconnect feature comprises a second conductive material, with a seam or an interface at a junction of the first and second conductive materials.
17 . The integrated circuit device of claim 16 , wherein the junction of the first and second interconnect features is at least 1 nanometer (nm) below a top surface of the first dielectric material.
18 . An integrated circuit comprising:
a first interconnect layer comprising a first dielectric layer and a first conductive interconnect feature within the first dielectric layer, wherein a top surface of the first conductive interconnect feature is at least 1 nanometer (nm) below a top surface of the first dielectric layer;
a second interconnect layer above the first interconnect layer, the second interconnect layer comprising a second dielectric layer and a second conductive interconnect feature within the second dielectric layer; and
a conformal layer separating at least a section of the first dielectric layer from a corresponding section of the second dielectric layer,
wherein a portion of a bottommost surface of the second conductive interconnect feature is directly on a portion of the conformal layer and is directly above a portion of the first conductive interconnect feature, such that the conformal layer is between the portion of the bottommost surface of the second conductive interconnect feature and the portion of the first conductive interconnect feature.
19 . The integrated circuit of claim 18 , wherein:
a portion of the bottommost surface of the second interconnect feature is directly on the top surface of the first dielectric layer.
20 . The integrated circuit of claim 18 , further comprising a third conductive interconnect feature within the second dielectric layer, wherein at least part of the third conductive interconnect feature is directly on the first conductive interconnect feature, such that the third conductive interconnect feature contacts the first conductive interconnect feature below the top surface of the first dielectric layer.