Frequency/phase-shift-keying for back-channel serdes communication
Methods, integrated circuits and computer-readable media for communicating back-channel data over a data link by modulating the phase or frequency of a clock signal of a data signal transmitted over the data link. Slow modulation of the clock signal allows it to be detected and extracted by a receiver without affecting the integrity or bit rate of the data signal. Some embodiments allow the functionality to be implemented without the use of extra hardware in the transmitter or receiver or either.
1. An integrated circuit (IC) for communicating back-channel data over a SerDes data link, comprising:
a digital modulator for receiving back-channel data and modulating at least one clock signal to encode the back-channel data, producing a modulated clock signal; and
a transmitter for receiving a data input signal and the modulated clock signal and transmitting over the SerDes data link a data output signal encoded by the modulated clock signal.
2. The IC of claim 1 , wherein the digital modulator encodes the back-channel data using frequency-shift keying.
3. The IC of claim 1 , wherein the digital modulator encodes the back-channel data using phase-shift keying.
4. The IC of claim 1 , wherein the digital modulator modulates the clock signal at a global clock source.
5. The IC of claim 1 , wherein:
the data output signal has at least two lanes;
the clock input signal comprises a clock tree having two or more branches for encoding two or more lanes of the data output signal; and
the digital modulator modulates one or more branches of the clock tree.
6. The IC of claim 5 , wherein the digital modulator applies the same modulation to two or more branches of the clock tree.
7. The IC of claim 5 , wherein the digital modulator applies different modulation to two or more branches of the clock tree.
8. The IC of claim 1 , wherein the digital modulator modulates the clock signal at a phase interpolator.
9. The IC of claim 1 , wherein the modulation applied by the digital modulator introduces clock signal delays greater than 0.1 unit interval.
10. The IC of claim 1 , wherein the modulation applied by the digital modulator introduces clock signal delays having a duration at least as long as two sampling periods of a SerDes receiver.
11. The IC of claim 10 , further comprising a receiver configured to receive the data output signal from the SerDes data link, capture multiple samples of the data output signal, and average the multiple samples in order to detect clock modulation levels in the data output signal.
12. The IC of claim 1 , wherein the digital modulator comprises a processor configured to execute instructions for performing the modulation.
13. The IC of claim 1 , wherein the SerDes data link comprises an electrical link.
14. The IC of claim 1 , wherein the SerDes data link comprises an optical link.
15. An integrated circuit (IC) for communicating back-channel data over a SerDes data link, comprising:
a receiver for receiving a data signal over the SerDes data link, detecting modulation of at least one clock signal encoding the data signal, and extracting back-channel data from the modulation of the clock signal based on a predetermined modulation scheme.
16. A method for communicating back-channel data over a SerDes data link comprising the steps of:
modulating a clock signal to encode back-channel data, producing a modulated clock signal; and
transmitting over the SerDes data link a data output signal encoded by the modulated clock signal.
17. The method of claim 16 , wherein the step of modulating comprises modulating the clock signal at a global clock source.
18. The method of claim 16 , wherein:
the data output signal has at least two lanes;
the clock signal comprises a clock tree having two or more branches for encoding two or more lanes of the data output signal; and
the step of modulating comprises modulating one or more branches of the clock tree.
19. The method of claim 16 , wherein the step of modulating comprises modulating the clock signal at a phase interpolator.
20. A non-transitory computer-readable medium containing instructions enabling one or more processors of an electronic communication system to execute the steps of:
modulating a clock signal to encode back-channel data, producing a modulated clock signal; and
transmitting over a SerDes data link a data output signal encoded by the modulated clock signal.