Transmitting clock reference over reverse channel in a bidirectional serial link
A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.
1. A clock recovery circuit for a serializer/deserializer comprising:
a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream;
a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and
a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.
2. The clock recovery circuit of claim 1 , wherein the controller is configured to perform device initialization.
3. The clock recovery circuit of claim 1 , wherein the controller is configured to enable the clock detector after initialization.
4. The clock recovery circuit of claim 1 , wherein the clock reference data comprises a predetermined pattern of ones and zeros.
5. The clock recovery circuit of claim 1 , wherein the phase lock loop further comprises a second detector configured to receive the serial data stream and to detect a second phase.
6. The clock recovery circuit of claim 5 , wherein the second detector comprises a Hogge phase detector.
7. The clock recovery circuit of claim 5 , wherein the controller is configured to disable the first detector and enable the second detector based on the first detector being locked.
8. The clock recovery circuit of claim 5 , wherein the controller is configured to start transmitting data after enabling the second detector.
9. The clock recovery circuit of claim 1 , further comprising a charge pump configured to receive an output of the first detector.
10. The clock recovery circuit of claim 9 , further comprising a low pass filter configured to receive an output of the charge pump.
11. The clock recovery circuit of claim 9 , wherein the controller is configured to enable the charge pump and the first detector based on the clock detector generating the clock detect signal.
12. The clock recovery circuit of claim 1 , wherein the phase lock loop further comprises a voltage controlled oscillator configured to selectively communicate with an output of the first detector and to output a clock signal.
13. The clock recovery circuit of claim 12 , wherein the phase lock loop further comprises a frequency divider configured to divide the clock signal and to output a divided clock signal to the first detector.
14. The clock recovery circuit of claim 12 , wherein the voltage controlled oscillator is configured to operate in either an open loop mode or a closed loop mode.
15. The clock recovery circuit of claim 12 , wherein upon startup, the controller is configured to disable a charge pump coupled to the first detector, and to configure the voltage controlled oscillator in an open loop mode.
16. A clock recovery circuit for a serializer/deserializer comprising:
a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream;
a phase lock loop including a detector configured to receive the serial data stream and to operate as a phase/frequency detector, or a phase detector, the phase lock loop further comprises a voltage controlled oscillator configured to selectively communicate with an output of the detector and to output a clock signal; and
a controller configured to receive the clock detect signal and to selectively enable the detector based on the clock detect signal.
17. A method of manufacturing a clock recovery circuit for a serializer/deserializer comprising:
configuring a clock detector to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, and configuring the clock detector includes configuring the clock detector to output a clock detect signal in response to detecting the clock reference data in the serial data stream;
configuring a phase lock loop including a first detector to receive the serial data stream and to detect phase and frequency; and
configuring a controller to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.
18. The method of claim 17 , wherein configuring the controller includes configuring the controller to perform device initialization.
19. The method of claim 17 , wherein configuring the controller includes configuring the controller to enable the clock detector after initialization.
20. The method of claim 17 , wherein configuring the clock detector includes configuring the clock detector to receive the serial data stream including the clock reference data comprising a predetermined pattern of ones and zeros.
21. The method of claim 17 , wherein configuring the phase lock loop further comprises configuring a second detector to receive the serial data stream and to detect a second phase.
22. The method of claim 21 , wherein configuring the second detector comprises configuring a Hogge phase detector.
23. The method of claim 21 , wherein configuring the controller includes configuring the controller to disable the first detector and enable the second detector based on the first detector being locked.
24. The method of claim 21 , wherein configuring the controller includes configuring the controller to start transmitting data after enabling the second detector.
25. The method of claim 17 , further comprising configuring a charge pump to receive an output of the first detector.
26. The method of claim 25 , further comprising configuring a low pass filter to receive an output of the charge pump.
27. The method of claim 25 , wherein configuring the controller includes configuring the controller to enable the charge pump and the first detector based on the clock detector generating the clock detect signal.
28. The method of claim 17 , wherein configuring the phase lock loop further comprises configuring a voltage controlled oscillator to selectively communicate with an output of the first detector and to output a clock signal.
29. The method of claim 28 , wherein configuring the phase lock loop further comprises configuring a frequency divider to divide the clock signal and to output a divided clock signal to the first detector.
30. The method of claim 28 , wherein configuring the voltage controlled oscillator includes configuring the voltage controlled oscillator to operate in either an open loop mode or a closed loop mode.
31. The method of claim 28 , wherein configuring the controller includes configuring the controller, upon startup, to disable a charge pump coupled to the first detector, and to place the voltage controlled oscillator in an open loop mode.