IP Library Granted Patent US 10,153,985
Granted Patent B2
US 10,153,985 · App. 15/435,952 · Granted Dec 11, 2018

Dragonfly processor interconnect network

Inventors: John Kim (Seattle, WA); Dennis C. Abts (Chippewa Falls, WI); Steven L. Scott (Chippewa Falls, WI); William J. Dally (Palo Alto, CA)
Assignees: Intel Corporation; The Board of Trustees of the Leland Stanford Junior University
H04L49/15G06F9/45533G06F13/4027G06F13/4221G06F15/17375H04L45/58H04L49/70H04L45/28H04L49/1515
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Quick Facts
Patent No.
US 10,153,985
App. No.
15/435,952
Granted
Dec 11, 2018
Kind
B2
Abstract

A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.

Claims (25)

1. A multiprocessor computer system comprising a dragonfly processor interconnect network, the dragonfly processor interconnect network comprising:

a plurality of processor nodes;

a first plurality of routers, each router in the first plurality of routers directly coupled to a respective subset of the plurality of processor nodes, the routers in the first plurality of routers coupled to one another and arranged into a first group of routers in a plurality of groups of routers,

a second plurality of routers, each router in the second plurality of routers directly coupled to a respective subset of the plurality of processor nodes, the routers in the second plurality of routers coupled to one another and arranged into a second group of routers in a plurality of groups of routers;

wherein each group in the plurality of groups of routers is connected to each other group via a single respective direct connection, each of the direct connections comprises a respective global channel, and the routers route data using credit round-trip latency as an indicator of channel congestion.

2. The multiprocessor computer system of claim 1 , wherein each group acts as a high radix virtual router.

3. The multiprocessor computer system of claim 1 , wherein a virtual radix of each group is a product of a number of routers in each group multiplied by a sum of a number of processor nodes connected to each router plus a number of global channels in the group.

4. The multiprocessor computer system of claim 1 , wherein a number of routers per group is equal to twice a number of processor nodes per router, and wherein the number of processor nodes per router is equal to a number of channels per router connected to other groups.

5. The multiprocessor computer system of claim 1 , wherein a number of routers in a group is greater than twice a number of global channels per router.

6. The multiprocessor computer system of claim 1 , wherein a number of processor nodes per router is greater than a number of global channels per router.

7. The multiprocessor computer system of claim 1 , wherein the routers within a group are connected via a flattened butterfly network.

8. The multiprocessor computer system of claim 1 , wherein the router is to route data using selective virtual channel discrimination.

9. The multiprocessor computer system of claim 1 , wherein all minimal routes within the network traverse at most one global channel.

10. A method of operating a multiprocessor computer system, comprising:

communicating a message from a processor node to a router, the router coupled to a plurality of processor nodes;

communicating the message between two or more routers, the routers coupled to one another and arranged into a group, wherein the group is one of a plurality of groups of routers and each group is connected to each other group in the plurality of groups of routers via a respective global channel; and

communicating data between two groups of routers using a corresponding one of the global channels, wherein each group is connected to each other group of a network via a single respective direct connection, wherein the routers to route data using credit round-trip latency as an indicator of channel congestion.

11. The method of operating a multiprocessor computer system of claim 10 , wherein each group acts as a high radix virtual router.

12. The method of operating a multiprocessor computer system of claim 10 , wherein a virtual radix of each group is a product of a number of routers in each group multiplied by a sum of a number of processor nodes connected to each router plus a number of global channels in the group.

13. The method of operating a multiprocessor computer system of claim 10 , wherein a number of routers per group is equal to twice a number of processor nodes per router, and wherein the number of processor nodes per router is equal to a number of channels per router connected to other groups.

14. The method of operating a multiprocessor computer system of claim 10 , wherein a number of routers in a group is greater than twice a number of global channels per router.

15. The method of operating a multiprocessor computer system of claim 10 , wherein a number of processor nodes per router is greater than a number of global channels per router.

16. The method of operating a multiprocessor computer system of claim 10 , wherein the routers within a group are connected via a flattened butterfly network.

17. The method of operating a multiprocessor computer system of claim 10 , wherein the routers route data using selective virtual channel discrimination.

18. The method of operating a multiprocessor computer system of claim 10 , wherein all minimal routes within the network traverse at most one global channel.

Continuity (3)
Continuation 14583588 · Dec 27, 2014
Continuation 12195198 · Aug 20, 2008
Related Publication 20170353401A1 · Dec 7, 2017
Cited By (1)
US 12,418,475