Dual port tap router for asynchronous capture shift data register
This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a third embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and in response producing Capture and Update signals that are input to a Programmable Switch that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a fourth embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. Each of the embodiments may be augmented to include externally accessible Update and Capture input signals that can be selected to allow a tester to directly control the at-speed operations of a circuit. The improvements of the disclosure are achieved without requiring any additional IC pins beyond the 4 required TAP pins, except for examples showing use of additional data input pins (TDI or WPI signals), additional data output pins (TDO or WPO signals) or examples showing use of additional control input pins (Capture and Update signals). Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don't include the TAP improvements.
1. An integrated circuit comprising:
(a) a test data in (TDI) lead, a test data out (TDO) lead, a test clock (TCK) lead, a test mode select (TMS) lead, and a data register enable lead;
(b) a test access port (TAP) state machine having an input coupled to the TCK lead, an input coupled to the TMS lead, a ClockDR output, and a ShiftDR output;
(c) a command circuit having an input connected to the TCK lead, a data input connected to the TMS signal lead, and a control output;
(d) a data register having an input coupled to the TDI lead, an output coupled to the TDO lead, a ClockDR input, and a ShiftDR input; and
(e) a routing circuit having:
a control input coupled to the control output of the command circuit,
a ClockDR input coupled to the ClockDR output of the TAP state machine,
a ShiftDR input coupled to the ShiftDR output of the TAP state machine,
a data register enable input coupled to the data register enable lead,
a ClockDR output coupled to the ClockDR input of the data register, and
a ShiftDR output coupled to the ShiftDR input of the data register.
2. The integrated circuit of claim 1 including functional circuitry and the data register is coupled to the functional circuitry.
3. The integrated circuit of claim 1 including functional circuitry and the data register is a debug register coupled to the functional circuitry.
4. The integrated circuit of claim 1 including functional circuitry and the data register is a programming data register coupled to the functional circuitry.
5. The integrated circuit of claim 1 including instrumentation circuitry and the data register is an instrumentation data register coupled to the instrumentation circuitry.
6. The integrated circuit of claim 1 including functional circuitry having interconnects and the data register is a boundary register coupled to the interconnects and the functional circuitry.
7. The integrated circuit of claim 1 including functional circuitry and the data register is a boundary register coupled to the functional circuitry.
8. The integrated circuit of claim 1 including core circuitry having core interconnects and the data register is a core wrapper boundary register coupled to the core interconnects circuitry.
9. The integrated circuit of claim 1 including core system logic and the data register is a core wrapper boundary register coupled to the core system logic.
10. The integrated circuit of claim 1 including functional circuitry having interconnects and another integrated circuit having interconnects and the data register is a boundary register coupled to the interconnects of the functional circuitry and the other integrated circuit.
11. The integrated circuit of claim 1 including first core circuitry and second core circuitry separate from the integrated circuit and the data register is a core wrapper boundary register coupled between the two cores.
12. The integrated circuit of claim 1 including first core circuitry and second core circuitry separate from the integrated circuit, the first core circuitry and the second core circuitry being coupled together and the data register is a boundary register coupled between the first core circuitry and the second core circuitry.