Semiconductor device for driving data line by using different voltages
A semiconductor device may include an input/output block suitable for operating by using a first voltage in an input mode and a second voltage in an output mode, a common input/output line coupled to the input/output block, and a voltage level maintaining block suitable for driving the common input/output line to maintain a voltage level of a transmission signal by using the first voltage in the input mode and the second voltage in the output mode.
1. A semiconductor device, comprising:
an input/output circuit configured to operate by using a first voltage in an input mode and a second voltage in an output mode;
a common input/output coupled to the input/output circuit; and
a voltage level maintaining circuit configured to drive the common input/output line to maintain a voltage level of a transmission signal by using the first voltage lower than the second voltage in the input mode and the second voltage in the output mode based on a mode determination signal for determining the input mode and the output mode,
wherein the voltage level maintaining circuit includes:
a first latch circuit configured to operate by using the first voltage;
a second latch circuit configured to operate by using the second voltage; and
a selective couple circuit configured to couple one of the first and second latch circuits to the common input/output line based on the mode determination signal.
2. The semiconductor device of claim 1 , wherein the input/output circuit includes:
an input circuit configured to operate by using the first voltage; and
an output circuit configured to operate by using the second voltage.
3. The semiconductor device of claim 1 , further comprising:
a mode control circuit configured to generate the mode determination signal based on a first command signal related to the input mode and a second command signal related to the output mode.
4. The semiconductor device of claim 1 , further comprising:
a write driving circuit formed between the common input/output line, coupled to the input/output circuit, and a local input/output line coupled to a memory circuit where an internal write data signal is written to and an internal read data signal is read from.
5. A semiconductor device, comprising:
an input/output circuit configured to operate by using a first voltage in an input mode and a second voltage in an output mode;
a common input/output line coupled to the input/output circuit; and
a voltage level maintaining circuit configured to drive the common input/output line to maintain a voltage level of a transmission signal by using the first voltage lower than the second voltage in the input mode and the second voltage in the output mode based on a mode determination signal for determining the input mode and the output mode,
wherein the voltage level maintaining circuit includes:
a latch circuit coupled to the common input/output line; and
a selective supply circuit configured to supply one of the first and second voltages as a source voltage of the latch circuit based on the mode determination signal.
6. The semiconductor device of claim 5 , further comprising:
a mode control circuit configured to generate the mode determination signal based on a first command signal related to the input mode and a second command signal related to the output mode.
7. A semiconductor device, comprising:
a memory circuit where an internal write data signal is written to and an internal read data signal is read from;
a write path configured to operate by using a first voltage to transmit the internal write data signal corresponding to an external write data signal to the memory circuit;
a read path configured to operate by using a second voltage to transmit the internal read data signal to an outside; and
a voltage level maintaining circuit configured to drive the write path to maintain a voltage level of the internal write data signal by using the first voltage lower than the second voltage in a write mode and drive the read path to maintain a voltage level of the internal read data signal by using the second voltage in a read mode based on a mode determination signal for determining the write mode or the read mode,
wherein the first voltage is lower than the second voltage,
wherein the voltage level maintaining circuit includes:
a first latch circuit configured to operate by using the first voltage:
a second latch circuit configured to operate by using the second voltage: and
a selective coupling circuit configured to couple one of the first and second latch circuits to the first common input/output line based on the mode determination signal.
8. The semiconductor device of claim 7 , wherein the write path and the read path share a first common input/output line.
9. The semiconductor device of claim 8 , wherein the write path includes;
an input circuit configured to receive the external write data signal based on the first voltage;
said first common input/output line;
a second common input/output line configured to transmit the internal write data signal to the memory circuit; and
a write driving circuit configured to drive the second common input/output line based on the internal write data signal transmitted from the first common input/output line by using the first voltage.
10. The semiconductor device of claim 9 , wherein the read path includes:
said first and second common output lines;
a read amplification circuit configured to drive the first common input/output line based on the internal read data signal transmitted from the second common input/output line by using the second voltage; and
an output circuit configured to output the internal read data signal to the outside.
11. The semiconductor device of claim 7 , further comprising:
a mode control circuit configured to generate the mode determination signal based on a write command signal and a read command signal.
12. The semiconductor device of claim 7 , wherein the write path includes:
an input circuit configured to receive the external write data signal based on the first voltage;
a write input/output line configured to transmit the internal write data signal; a common input/output line configured to transmit the internal write data signal to the memory circuit; and
a write driving circuit configured to drive the common input/output line based on the internal write data signal transmitted from the write input/output line by using the first voltage.
13. The semiconductor device of claim 12 , wherein the read path includes:
said common input/output line;
a read input/output line configured to transmit the read data signal;
a read amplification circuit configured to drive the read input/output line based on the internal read data signal transmitted from the common input/output line by using the second voltage;
an output circuit configured to output the read data signal to the outside.
14. The semiconductor device of claim 13 , wherein the voltage level maintaining circuit includes:
a first latch circuit configured to operate by using the first voltage; and
a second latch circuit configured to operate by using the second voltage.
15. A semiconductor device, comprising:
a memory circuit where an internal write data signal is written to and an internal read data signal is read from;
a write path configured to operate by using a first voltage to transmit the internal write data signal corresponding to an external write data signal to the memory circuit;
a read path configured to operate by using a second voltage to transmit the internal read data signal to an outside; and
a voltage level maintaining circuit configured to drive the write path to maintain a voltage level of the internal write data signal by using the first voltage lower than the second voltage in a write mode and drive the read path to maintain a voltage level of the internal read data signal by using the second voltage in a read mode based on a mode determination signal for determining the write mode or the read mode,
wherein the first voltage is lower than the second voltage,
wherein the voltage level maintaining circuit includes:
a latch circuit coupled to the first common input/output line; and
a selective supply circuit configured to supply one of the first and second voltages as a source voltage of the latch circuit based on a mode determination signal.
16. The semiconductor device of claim 15 , further comprising:
a mode control circuit configured to generate the mode determination signal based on a write command signal and a read command signal.