Connection structure for vertical gate all around (VGAA) devices on semiconductor on insulator (SOI) substrate
A vertical gate all around (VGAA) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of VGAA nanowire devices including a NMOS and a PMOS device. The devices are formed on a semiconductor-on-insulator substrate. Each device comprises a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other serves as a source node. Each device further comprises a gate layer. The gate layer fully surrounds a vertical channel in the device. In one example, a CMOS circuit is formed with an oxide (OD) block layer that serves as a common bottom plate for the NMOS and PMOS devices. In another example, a CMOS circuit is formed with a top plate that serves as a common top plate for the NMOS device and the PMOS devices. In another example, a SRAM circuit is formed.
1. A vertical gate all around (VGAA) nanowire device circuit routing structure, the circuit routing structure comprising:
a plurality of VGAA nanowire devices including a NMOS VGAA nanowire device and a PMOS VGAA nanowire device, the VGAA nanowire devices being formed on a semiconductor-on-insulator (SOI) substrate, each of the VGAA nanowire devices comprising a bottom plate and a top plate, wherein one of the bottom and top plates serves as a drain node and the other of the bottom and top plates serves as a source node, each of the VGAA nanowire devices further comprising a gate layer, the gate layer comprising a high-K gate dielectric and a metal layer, the gate layer fully surrounding a vertical channel in the VGAA nanowire device and serving as a gate node; and
a CMOS circuit formed by the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the CMOS circuit comprising a common bottom plate shared by the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the common bottom plate electrically coupling the drain node of the NMOS VGAA nanowire device to the drain node of the PMOS VGAA nanowire device, the CMOS circuit further comprising two separate gate layers that collectively serve as a common gate for the NMOS VGAA nanowire device and the PMOS VGAA nanowire device to electrically connect the gate node of the NMOS VGAA nanowire device to the gate node of the PMOS VGAA nanowire device, the CMOS circuit further comprising a first top plate that serves as the source node for the NMOS VGAA nanowire device and a second top plate that serves as the source node for the PMOS VGAA nanowire device, the first top plate being electrically connected to a Vss conductor via a first contact formed over the first top plate, and the second top plate is electrically connected to a Vdd conductor via a second contact formed above the second top plate.
2. The VGAA nanowire device circuit routing structure of claim 1 , wherein the two separate gate layers are electrically connected by a gate contact.
3. The VGAA nanowire device circuit routing structure of claim 1 , further comprising a silicide layer formed on the common bottom plate.
4. The VGAA nanowire device circuit routing structure of claim 1 , wherein each of the first top plate and the second top plate comprises a silicide layer.
5. The VGAA nanowire device circuit routing structure of claim 1 , wherein the vertical channel in each of the NMOS VGAA nanowire device and the PMOS VGAA nanowire device comprises a Si-based or epi growth compound material and extends in length between corresponding source and drain nodes.
6. The VGAA nanowire device circuit routing structure of claim 5 , wherein the channel material of the PMOS VGAA nanowire device comprises the Si-based or epi growth compound material selected from a group comprising: SiGe, SiGeC, Ge, Si, a type III-V compound, or a combination of one or more of the foregoing materials.
7. The VGAA nanowire device circuit routing structure of claim 5 , wherein the channel material of the NMOS VGAA nanowire device comprises the Si-based or epi growth compound material selected from a group comprising: SiP, SiC, SiPC, Si, Ge, a type III-V compound, or a combination of one or more of the foregoing materials.
8. The VGAA nanowire device circuit routing structure of claim 5 , wherein the diameter or width of the nanowire vertical channel is less than 10 nm.
9. The routing structure of claim 5 , wherein each of the VGAA nanowire devices comprises a plurality of vertical nano-pillars that form channel regions extending between a common drain node and a common source node and being surrounded by a common gate node in the VGAA nanowire device.
10. A vertical gate all around (VGAA) nanowire device circuit routing structure, comprising:
a plurality of VGAA nanowire devices including a NMOS VGAA nanowire device and a PMOS VGAA nanowire device, the VGAA nanowire devices having been formed on a semiconductor-on-insulator (SOI) substrate, each VGAA nanowire device comprising a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other of the bottom and top plates serves as a source node, each VGAA nanowire device further comprising a gate layer, the gate layer comprising a high-K gate dielectric and a metal layer, the gate layer fully surrounding a vertical channel in the VGAA nanowire device and serving as a gate node; and
a CMOS circuit formed by the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the CMOS circuit further comprising a common top plate that includes a silicon-based block shared by the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the silicon-based block electrically coupling a drain node of the NMOS VGAA nanowire device to a drain node of the PMOS VGAA nanowire device, the CMOS circuit comprising two separate gate layers that collectively serve as a common gate for the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the CMOS circuit comprising a first bottom plate that serves as the source node for the NMOS VGAA nanowire device and a second bottom plate that serves as the source node for the PMOS VGAA nanowire device, wherein the first bottom plate is electrically connected to a Vss conductor and the second bottom plate is electrically connected to a Vdd conductor.
11. The VGAA nanowire device circuit routing structure of claim 10 , wherein the two separate gate layers are electrically connected by a gate contact.
12. The VGAA nanowire device circuit routing structure of claim 10 , wherein a silicide layer is formed on the first and second bottom plates and on the common top plate.
13. The VGAA nanowire device circuit routing structure of claim 10 , wherein the vertical channel in each VGAA nanowire device comprises a silicon-based material and extends lengthwise from a source region to a drain region in the VGAA nanowire device.
14. The VGAA nanowire device circuit routing structure of claim 10 , wherein
the first and second bottom plates are formed a first distance above the SOI substrate, and
the silicon-based block is formed a second distance above the SOI substrate, the second distance being greater than the first distance.
15. The VGAA nanowire device circuit routing structure of claim 10 , wherein each of the first bottom plate and the second bottom plate comprises a silicide layer.
16. The VGAA nanowire device circuit routing structure of claim 10 , wherein the vertical channel in each of the NMOS VGAA nanowire device and the PMOS VGAA nanowire device comprises a Si-based or epi growth compound material and extends from a source region to a drain region in the VGAA nanowire device.
17. The VGAA nanowire device circuit routing structure of claim 16 , wherein the channel material of the PMOS VGAA nanowire device comprises the Si-based or epi growth compound material selected from a group comprising: SiGe, SiGeC, Ge, Si, a type III-V compound, or a combination of one or more of the foregoing materials.
18. The VGAA nanowire device circuit routing structure of claim 16 , wherein the channel material of the NMOS VGAA nanowire device comprises the Si-based or epi growth compound material selected from a group comprising: SiP, SiC, SiPC, Si, Ge, a type III-V compound, or a combination of one or more of the foregoing materials.
19. The VGAA nanowire device circuit routing structure of claim 16 , wherein each of the VGAA nanowire devices comprises a plurality of vertical nano-pillars forming channel regions extending between a common drain node and a common source node and surrounded by a common gate node in the VGAA nanowire device.
20. A vertical gate all around (VGAA) nanowire device circuit routing structure, the circuit routing structure comprising:
a plurality of VGAA nanowire devices including a NMOS VGAA nanowire device and a PMOS VGAA nanowire device, the VGAA nanowire devices being formed on a semiconductor-on-insulator (SOI) substrate; and
a CMOS circuit formed by the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the CMOS circuit comprising a common bottom plate shared by the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the common bottom plate electrically coupling a drain node of the NMOS VGAA nanowire device to a drain node of the PMOS VGAA nanowire device, the CMOS circuit further comprising two separate gate layers that collectively serve as a common gate for the NMOS VGAA nanowire device and the PMOS VGAA nanowire device to electrically connect a gate node of the NMOS VGAA nanowire device to a gate node of the PMOS VGAA nanowire device, the CMOS circuit further comprising a first top plate that serves as a source node for the NMOS VGAA nanowire device and a second top plate that serves as a source node for the PMOS VGAA nanowire device, the first top plate being electrically connected to a Vss conductor via a first contact formed over the first top plate, and the second top plate is electrically connected to a Vdd conductor via a second contact formed above the second top plate.