Semiconductor device and manufacturing method thereof
A field effect transistor includes a channel layer made of a semiconductor and a metal gate structure. The metal gate structure includes a gate dielectric layer, a barrier layer formed on the gate dielectric layer, a work function adjustment layer formed on the barrier layer and made of one of Al and TiAl, a blocking layer formed on the work function adjustment layer and made of TiN, and a body metal layer formed on the blocking layer and made of W. A gate length over the channel layer is in a range from 5 nm to 15 nm, and a thickness of the first conductive layer is in a range of 0.2 nm to 3.0 nm. A range between a largest thickness and a smallest thickness of the first conductive layer is more than 0% and less than 10% of an average thickness of the first conductive layer.
1. A semiconductor device, comprising a field effect transistor, wherein:
the FET includes a channel layer made of a semiconductor and a metal gate structure,
the metal gate structure includes:
a gate dielectric layer;
a barrier layer formed on the gate dielectric layer; and
a work function adjustment layer formed on the barrier layer,
a thickness of the barrier layer is in a range of 0.2 nm to 3.0 nm,
the barrier layer includes a layer made of TiN doped with Si, and
a range between a largest thickness and a smallest thickness of the barrier layer is more than 0% and less than 10% of an average thickness of the barrier layer.
2. The semiconductor device of claim 1 , wherein the metal gate structure further includes a body metal layer formed over the work function adjustment layer.
3. The semiconductor device of claim 2 , wherein the metal gate structure further includes a blocking layer between the work function adjustment layer and the body metal layer.
4. The semiconductor device of claim 2 , wherein the work function adjustment layer includes one of Al and TiAl.
5. The semiconductor device of claim 2 , wherein work function adjustment layer is Al.
6. A semiconductor device, comprising a field effect transistor, wherein:
the FET includes a channel layer made of a semiconductor and a metal gate structure,
the metal gate structure includes:
a gate dielectric layer;
a barrier layer formed on the gate dielectric layer; and
a work function adjustment layer formed on the barrier layer,
a thickness of the barrier layer is in a range of 0.2 nm to 3.0 nm,
the barrier layer includes a layer made of TiN doped with Si, and
a gate length over the channel layer is in a range from 5 nm to 15 nm.
7. A semiconductor device, comprising a field effect transistor, wherein:
the FET includes a channel layer made of a semiconductor and a metal gate structure,
the metal gate structure includes:
a gate dielectric layer;
a barrier layer formed on the gate dielectric layer; and
a work function adjustment layer formed on the barrier layer,
a thickness of the barrier layer is in a range of 0.2 nm to 3.0 nm,
the barrier layer includes a TiN layer and a TaN layer formed on the TiN layer, and
a range between a largest thickness and a smallest thickness of the barrier layer is more than 0% and less than 10% of an average thickness of the barrier layer.
8. The semiconductor device of claim 7 , wherein a thickness of the TaN layer is in a range from 0.1 nm to 2.0 nm.
9. The semiconductor device of claim 7 , wherein a gate length over the channel layer is in a range from 5 nm to 15 nm.
10. The semiconductor device of claim 7 , wherein the metal gate structure further includes a body metal layer formed over the work function adjustment layer.
11. The semiconductor device of claim 10 , wherein the metal gate structure further includes a blocking layer between the work function adjustment layer and the body metal layer.
12. The semiconductor device of claim 10 , wherein the work function adjustment layer includes one of Al and TiAl.
13. A method of forming a barrier layer disposed between a gate dielectric layer and a work function adjustment layer in a gate structure, the method comprising:
forming a TiN layer over the gate dielectric layer;
reducing a thickness of the TiN layer;
forming a TaN layer over the TiN layer of which thickness is reduced; and
reducing a thickness of the TaN layer.
14. The method of claim 13 , wherein a thickness of the barrier layer is in a range of 0.2 nm to 3.0 nm.
15. The method of claim 13 , wherein a range between a largest thickness and a smallest thickness of the barrier layer is more than 0% and less than 10% of an average thickness of the barrier layer.
16. The method of claim 13 , wherein the TiN layer and TaN layer are formed by atomic layer deposition.
17. The method of claim 13 , wherein the thickness of the TaN layer is reduced by plasma etching using WCl 5 gas.
18. The method of claim 17 , wherein a thickness of the TaN layer after reducing the thickness is in a range from 0.1 nm to 2.0 nm.
19. The method of claim 13 , wherein the thickness of the TiN layer is reduced by chemical etching using a HCl and H 2 O 2 solution.
20. The method of claim 19 , wherein a thickness of the TiN layer after reducing the thickness is in a range from 0.1 nm to 2.0 nm.