Manufacturing method of semiconductor structure
The present disclosure provides a manufacturing method for the semiconductor structure, including forming a bottom metal layer including copper, forming a planar memory layer over the bottom metal layer, forming an electrode over the planar memory layer by a self-aligning operation, and defining a memory cell by patterning the planar memory layer.
1. A manufacturing method of a semiconductor structure, comprising:
forming a bottom metal layer comprising copper;
forming a planar memory layer over the bottom metal layer;
forming an electrode over the planar memory layer having a first width by a self-aligning operation, the self-aligning operation comprising:
forming an etch stop over the planar memory layer;
patterning the etch stop to form a first opening;
forming a spacer with a predetermined width in the first opening, laterally covering a sidewall of the etch stop thereby forming a second opening narrower than the first opening; and
defining a memory cell having a second width by patterning the planar memory layer, wherein the first width is smaller than the second width.
2. The manufacturing method in claim 1 , wherein the self-aligning operation further comprises:
forming the electrode in the second opening.
3. The manufacturing method in claim 2 , wherein the forming the electrode comprises an etch back operation.
4. The manufacturing method in claim 3 , wherein the forming the electrode further comprises performing a planarization operation before the etch back operation.
5. The manufacturing method in claim 3 , wherein the etch back operation comprises adopting an etchant having a selectivity between TiN and SiN.
6. The manufacturing method in claim 2 , wherein the forming the electrode comprises:
depositing an electrode layer in the second opening by an atomic layer deposition; and
etching back the electrode layer to reach a height less than one half a height of the second opening.
7. The manufacturing method in claim 1 , further comprising forming an upper metal layer in contact with the electrode.
8. A manufacturing method of a semiconductor structure, comprising:
forming a bottom metal layer;
forming a planar memory layer over the bottom metal layer;
forming an electrode over the planar memory layer by a self-aligning operation, the self-aligning operation comprising:
forming an etch stop over the planar memory layer;
patterning a mask layer having an opening over the etch stop;
forming a spacer at a sidewall of the opening of the mask layer after patterning the mask layer; and
forming the electrode in a region surrounded by the spacer; and
defining a memory cell by patterning the planar memory layer.
9. The manufacturing method in claim 8 , wherein the bottom metal layer comprises copper.
10. The manufacturing method in claim 8 , wherein the forming the electrode comprises:
depositing an electrode layer in the opening; and
etching back the electrode layer to reach a height less than one half a height of the opening.
11. The manufacturing method in claim 10 , further comprising performing a chemical mechanical polishing operation before the etching back the electrode layer.
12. The manufacturing method in claim 8 , further comprising forming an upper metal layer in contact with the electrode.
13. The manufacturing method in claim 12 , wherein the electrode comprises a ripple surface in connection with the upper metal layer.
14. The manufacturing method in claim 8 , wherein the forming the spacer at the sidewall of the mask layer defines a width of the electrode subsequently formed.
15. The manufacturing method in claim 8 , further comprising forming a nitride layer surrounding the electrode.
16. The manufacturing method in claim 15 , further comprising forming a carbide layer surrounding the nitride layer and the electrode.
17. A manufacturing method of a semiconductor structure, comprising:
forming a bottom metal layer;
forming a planar memory layer over the bottom metal layer;
forming an electrode over the planar memory layer by a self-aligning operation, the self-aligning operation comprising:
forming an etch stop over the planar memory layer;
patterning a mask layer having an opening over the etch stop;
forming a first spacer at a sidewall defining the opening of the mask layer;
forming the electrode in a region surrounded by the first spacer; and
forming a second spacer over the electrode and the first spacer; and
defining a memory cell by patterning the planar memory layer.
18. The manufacturing method in claim 17 , wherein the bottom metal layer comprises copper.
19. The manufacturing method in claim 17 , wherein the forming the electrode comprises:
depositing an electrode layer in the opening; and
etching back the electrode layer to reach a height less than a height of the opening.
20. The manufacturing method in claim 19 , further comprising performing a chemical mechanical polishing operation before the etching back the electrode layer.