Reference disturbance mitigation in successive approximation register analog to digital converter
The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.
1. A Successive Approximation Register (SAR) Analog to Digital Converter (ADC) comprising:
a comparator;
a capacitor array coupled to an input of the comparator;
a fine reference connection;
a rough reference connection;
a switch array; and
a SAR sequencer configured to:
activate the switch array to couple a current bit capacitor of the capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by the comparator; and
activate the switch array to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection.
2. The SAR ADC of claim 1 , wherein coupling the previous bit capacitor to the fine reference connection includes simultaneously coupling a group of previous bit capacitors while the current bit capacitor is coupled to the rough reference connection.
3. The SAR ADC of claim 2 , wherein the group of previous bit capacitors includes a most significant bit (MSB) capacitor.
4. The SAR ADC of claim 2 , wherein the group of previous bit capacitors includes a specified number of largest capacitors in the capacitor array.
5. The SAR ADC of claim 1 , wherein the SAR sequencer does not cause the switch array to couple a least significant bit (LSB) capacitor to the fine reference.
6. The SAR ADC of claim 1 , wherein the SAR sequencer does not cause the switch array to couple a specified number of smallest capacitors to the fine reference.
7. The SAR ADC of claim 1 , wherein the fine reference connection includes a fine positive reference connection, a fine negative reference connection, or combinations thereof.
8. The SAR ADC of claim 1 , wherein the rough reference connection includes a rough positive reference connection, a rough negative reference connection, or combinations thereof.
9. The SAR ADC of claim 1 , wherein the current bit capacitor and the previous bit capacitor are positioned on separate SAR ADC cores and the SAR sequencer is configured as a multi-core SAR controller.
10. The SAR ADC of claim 1 , wherein capacitors of the capacitor array are coupled to the fine reference to avoid charge related disturbances associated with charge flow occurring across the rough connection during bit determinization by the comparator.
11. A method comprising:
activating, in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC), a switch array to couple a current bit capacitor of a capacitor array to a rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator; and
activating the switch array to couple a previous bit capacitor of the capacitor array to a fine reference connection while the current bit capacitor is coupled to the rough reference connection.
12. The method of claim 11 , wherein coupling the previous bit capacitor to the fine reference connection includes simultaneously coupling a group of previous bit capacitors while the current bit capacitor is coupled to the rough reference connection.
13. The method of claim 12 , wherein the group of previous bit capacitors includes a most significant bit (MSB) capacitor.
14. The method of claim 12 , wherein the group of previous bit capacitors includes a specified number of largest capacitors in the capacitor array.
15. The method of claim 11 , wherein the switch array does not couple a least significant bit (LSB) capacitor to the fine reference.
16. The method of claim 11 , wherein the switch array does not couple a specified number of smallest capacitors to the fine reference.
17. The method of claim 11 , wherein the fine reference connection includes a fine positive reference connection, a fine negative reference connection, or combinations thereof.
18. The method of claim 11 , wherein the rough reference connection includes a rough positive reference connection, a rough negative reference connection, or combinations thereof.
19. The method of claim 11 , wherein the current bit capacitor and the previous bit capacitor are positioned on separate SAR ADC cores.
20. The method of claim 11 , wherein capacitors of the capacitor array are coupled to the fine reference to avoid charge related disturbances associated with charge flow occurring across the rough connection during bit determinization by the comparator.