Double affine mapped S-box hardware accelerator
A processing system includes a memory and a cryptographic accelerator module operatively coupled to the memory, the cryptographic accelerator module employed to implement a byte substitute operation by performing: a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence.
1. A processing system for performing a cryptographic operation comprising a byte substitution operation, the processing system comprising:
a memory device;
a cryptographic accelerator module operatively coupled to the memory device, the cryptographic accelerator module to implement the byte substitute operation by performing:
a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, wherein the first mapped affine transformation is represented by a first mapped affine transformation matrix produced by multiplying a first mapping matrix and a first transformation matrix,
an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and
a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence.
2. The processing system of claim 1 , wherein the first transformation matrix is associated with a pair of reduction polynomials of a finite field.
3. The processing system of claim 1 , wherein at least one of the input bit sequence and the output bit sequence is provided by an element of a finite prime-field, and wherein the first mapping matrix represents a mapping from the finite prime-field to a composite-field of the finite prime-field.
4. The processing system of claim 3 , wherein the finite prime-field is represented by a GF(2 8 ) Galois field.
5. The processing system of claim 3 , wherein the composite-field is represented by a GF(2 4 ) 2 Galois field.
6. The processing system of claim 1 , wherein the second mapped affine transformation is represented by a second mapped affine transformation matrix produced by multiplying a second mapping matrix and a second transformation matrix.
7. The processing system of claim 1 , wherein the processing system is employed to perform cryptographic operation is represented by one of: an SMS4 encryption operation or an SMS4 decryption operation.
8. The processing system of claim 1 , wherein the processing system is implemented as a System-on-Chip (SoC).
9. A method, comprising: performing, by a cryptographic accelerator module, a byte substitution operation comprising:
a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, wherein the first mapped affine transformation is represented by a first mapped affine transformation matrix produced by multiplying a first mapping matrix and a first transformation matrix,
an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and
a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence; and
performing a cryptographic operation using the output bit sequence.
10. The method of claim 9 , wherein the first transformation matrix is associated with a pair of reduction polynomials of a finite field.
11. The method of claim 9 , wherein at least one of the input bit sequence and the output bit sequence is provided by an element of a finite prime-field, and wherein the first mapping matrix represents a mapping from the finite prime-field to a composite-field of the finite prime-field.
12. The method of claim 11 , wherein the finite prime-field is represented by a GF(2 8 ) Galois field.
13. The method of claim 11 , wherein the composite-field is represented by a GF(2 4 ) 2 Galois field.
14. The method of claim 9 , further comprising:
performing a cryptographic operation using the output bit sequence.