Tap domain selection circuit with AUX buffers and multiplexer
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49 , provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8 .
1. An integrated circuit comprising:
A. plural TAP domains, each domain having a TDI input terminal, a TDO output terminal, a TCK input terminal, a TMS input terminal, and a RCK output terminal; and
B. a TAP domain selection circuit, the selection circuit having a separate set of outputs and at least one input for each TAP domain, each set including a TDI output connected to a TDI input terminal, a TDO input connected to a TDO output terminal, a TCK output connected to a TCK input terminal, a TMS output connected to a TMS input terminal, and a RCK input connected to a RCK output terminal, the selection circuit including an interface select circuit including:
i. an instruction control bus input;
ii. a TDI output lead coupled to the TDI output of each set;
iii. an AUXOUT 1 output lead;
iv. an AUXIN 1 input lead;
v. an AUX I/O 1 or TDI lead;
vi. a first buffer having an input connected to the AUXOUT 1 output lead, a control input connected to the instruction control bus input, and an output connected to the AUX I/O 1 or TDI lead;
vii. a second buffer having an input connected to the AUX I/O 1 or TDI lead, and an output connected to the AUXIN 1 input lead;
viii. a multiplexer having one lead connected to the output of the second buffer, a control input connected to the instruction control bus input, and an output connected to the TDI output lead; and
ix. an instruction register having an input coupled to the TDI output lead and an instruction control output coupled to the instruction control bus input.
2. The integrated circuit of claim 1 in which the interface selection circuit also has:
i. a first lead selectively carrying a TDI signal,
ii. a second lead selectively carrying a TDO signal,
iii. a third lead selectively carrying a TMS signal, and
iv. a fourth lead selectively carrying a RCK signal.
3. The integrated circuit of claim 1 in which the interface selection circuit also has:
i. a first lead selectively carrying a TDI/TDO signal or a TDO signal,
ii. a second lead selectively carrying an AUX I/O 2 signal or a TMS signal, and
iii. a third lead selectively carrying a TMS/RCK signal or a RCK signal.
4. The integrated circuit of claim 1 in which the TCK output of the selection circuit is common to all sets of outputs and at least one input.