IP Library Granted Patent US 10,163,689
Granted Patent B2
US 10,163,689 · App. 15/384,076 · Granted Dec 25, 2018

Integrated circuit with conductive line having line-ends

Inventors: Chih-Yuan Ting (Taipei, TW); Jyu-Horng Shieh (Hsin-Chu, TW); Pei-Wen Huang (New Taipei, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L21/76816H01L21/0332H01L21/76895H01L21/823475H01L21/823871H01L23/5283H01L23/485H01L23/53233H01L23/53238H01L2924/0002
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,163,689
App. No.
15/384,076
Granted
Dec 25, 2018
Kind
B2
Abstract

A semiconductor device is disclosed, including a plurality of conductive features disposed over a substrate. A dielectric layer separates the conductive features. A conductive line is provided, connecting a subset of the conductive features. The conductive line includes a line-like portion and a line-end portion.

Claims (43)

1. A semiconductor device comprising:

a plurality of conductive features over a substrate;

a dielectric layer separating the conductive features; and

a conductive line connecting a subset of the conductive features, the conductive line including:

a line-like portion having a first length and a first width; and

a line-end portion connecting to an end of the line-like portion and disposed over one or more conductive features of the subset of the conductive features, wherein the line-end portion has a second width, larger than the first width, wherein the line-end portion has a second length, smaller than the first length.

2. The device of claim 1 , wherein the line-end portion of the conductive line is centered with respect to the end of the line-like portion.

3. The device of claim 1 , wherein the line-end portion of the conductive line, having a larger width than the first width of the line-like portion, is not centered with respect to the end of the line-like portion.

4. The device of claim 1 , wherein the line-end portion has a rectangular shape.

5. The device of claim 1 , wherein the plurality of conductive features extends through the dielectric layer.

6. The device of claim 1 , further comprising a hard mask (HM) layer disposed over the dielectric layer, wherein the conductive line is formed within the dielectric layer and the HM layer.

7. A semiconductor device comprising:

a substrate;

a first set of conductive features formed over the substrate;

a second set of conductive features formed over the substrate;

a first dielectric layer separating the first set of conductive features and the second set of conductive features;

a second dielectric layer formed over the first dielectric layer; and

a hard mask (HM) layer formed over the second dielectric layer, wherein the HM layer and the second dielectric layer comprise a line-end opening and a line-like opening, wherein the line-end opening is aligned to the first set of conductive features, wherein the line-end opening exposes the first set of conductive features, wherein the line-end opening connects with the line-like opening at a first end of the line-like opening, wherein the line-like opening has a first width and the line-end opening has a second width greater than the first width, wherein the line-like opening has a first length and the line-end opening has a second length smaller than the first length.

8. The device of claim 7 , further comprising a conductive line connecting the first set of conductive features and the second set of conductive features.

9. The device of claim 8 , wherein the conductive line is disposed in a trench within the second dielectric layer.

10. The device of claim 7 , wherein the line-like opening is aligned to the second set of conductive features.

11. The device of claim 7 , wherein the line-end opening has a rectangular shape.

12. The device of claim 7 , comprising a second line-end opening connected with the line-like opening at a second end of the line-like opening.

13. The device of claim 7 , wherein the HM layer includes a stack of layers, comprising:

a bottom titanium nitride layer;

an anti-reflection coating (ARC) layer formed over the bottom titanium nitride layer; and

a top titanium nitride layer formed over the ARC layer.

14. A semiconductor device comprising:

a substrate;

a first dielectric layer formed over the substrate;

a second dielectric layer formed over the first dielectric layer;

a set of conductive features extending through the first and second dielectric layers;

a third dielectric layer formed over the second dielectric layer; and

a hard mask (HM) layer formed over the third dielectric layer, wherein a trench is formed within the third dielectric layer and the HM layer, the trench comprising a line-like opening and two line-end openings connecting with the line-like opening at respective ends of the line-like opening, wherein the two line-end openings are aligned to a first subset of the set of conductive features, wherein the two line-end openings expose the first subset of the set of conductive features, wherein the line-like opening has a first width and the two line-end openings each have a second width greater than the first width, wherein the line-like opening has a first length and the two line-end openings each have a second length smaller than the first length.

15. The device of claim 14 , wherein the trench is filled with conductive material to form a conductive line.

16. The device of claim 15 , wherein the conductive line connects at least two conductive features within the set of conductive features.

17. The device of claim 14 , wherein the line-like opening is aligned to a second subset of the set of conductive features.

18. The device of claim 14 , wherein a length and a width of each line-end opening is the same.

19. The device of claim 14 , wherein the respective ends of the line-like opening abut respective sides of each of the line-end openings.

20. The device of claim 14 , wherein the HM layer includes a stack of layers, comprising:

a bottom titanium nitride layer;

an anti-reflection coating (ARC) layer formed over the bottom titanium nitride layer; and

a top titanium nitride layer formed over the ARC layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2017
From: HUANG, PEI-WEN; TING, CHIH-YUAN; SHIEH, JYU-HORNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 041426/0469 →
Continuity (2)
Division 14104917 · Dec 12, 2013
Related Publication 20170098574A1 · Apr 6, 2017
Cited By (1)
US 12,610,801