Semiconductor device and a method for fabricating the same

1. A method of manufacturing a semiconductor device, the method comprising:

forming a structure including a first gate structure, a first source/drain region and a first insulating layer disposed over the first source/drain region over a substrate, wherein the first gate structure extends in a first direction, and the first gate structure includes:

a first gate electrode,

a first cap insulating layer disposed over the first gate electrode,

first sidewall spacers disposed on opposing side faces of the first gate electrode and directly on opposing side faces of the first cap insulating layer, and

second sidewall spacers disposed on the first sidewall spacers;

after the forming the structure, recessing the first cap insulating layer and the second sidewall spacers, and recessing the first sidewall spacers, thereby forming a first recessed space; and

forming a first protective layer in the first recessed space, wherein:

the first recessed space has a π-shape having a head portion above the first cap insulating layer and the second sidewall spacers and two leg portions above the first sidewall spacers in a cross section along a second direction perpendicular to the first direction, and

the first protective layer has a π-shape having a head portion and two leg portions in a cross section along the second direction.

2. The method of claim 1 , wherein the first cap insulating layer is made of a same material as the second sidewall spacers and is made of a different material as the first sidewall spacers.

3. The method of claim 2 , wherein the first cap insulating layer and the second sidewall spacers are made of a silicon nitride based material.

4. The method of claim 3 , wherein the first sidewall spacers are made of a silicon oxide based material.

5. The method of claim 3 , wherein the first sidewall spacers are made of at least one of SiOC and SiOCN.

6. The method of claim 1 , wherein the first protective layer is made of at least one of aluminum nitride, aluminum oxynitride, aluminum oxide, titanium oxide, zirconium oxide.

7. The method of claim 1 , wherein the recessing the first cap insulating layer and the second sidewall spacers is performed before the recessing the first sidewall spacers.

8. The method of claim 1 , wherein the recessing the first cap insulating layer and the second sidewall spacers is performed after the recessing the first sidewall spacers.

9. The method of claim 1 , further comprising, after the forming the first protective layer:

removing a part of the first insulating layer above the source/drain region, thereby forming a contact hole; and

filling the contact hole with a conductive material;

recessing the filled conductive material; and

forming a second insulating layer over the recessed conductive material,

wherein when forming the contact hole, the first cap insulating layer is not etched.

10. The method of claim 9 , wherein the second insulating layer is made of at least one of SiOC, SiC and SiOCN.

11. A method of manufacturing a semiconductor device, the method comprising:

forming a structure including a first gate structure, a second gate structure, a first source/drain region disposed in an area between the first gate structure and the second gate structure, and a first insulating layer disposed over the first source/drain region and between the first gate structure and the second gate structure over a substrate, the first gate structure including a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and first etch-stop layers disposed on the first sidewall spacers, the second gate structure including a second gate electrode, a second cap insulating layer disposed over the second gate electrode, second sidewall spacers disposed on opposing side faces of the second gate electrode and the second cap insulating layer and second etch-stop layers disposed on the second sidewall spacers, the first and second gate structures extending in a first direction;

after the forming the structure, recessing the first and second cap insulating layers and the first and second etch-stop layers, and recessing the first and second sidewall spacers, thereby forming a first recessed space above the first gate electrode and a second recessed space above the second gate electrode; and

forming a first protective layer in the first recessed space and a second protective layer in the second recessed space, wherein:

upper surfaces of the recessed first and second cap insulating layers are located at a level lower than an upper surface of the first insulating layer,

upper surfaces of the recessed first and second sidewall spacers are located at a level higher than an upper surface of the first gate electrode,

each of the first and second recessed spaces has a π-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction, and

each of the first and second protective layers has a π-shape having a head portion and two leg portions in a cross section along the second direction.

12. The method of claim 11 , wherein the first and second cap insulating layers are made of a same material as the first and second etch-stop layers and are made of a different material as the first and second sidewall spacers.

13. The method of claim 12 , wherein:

the first and second cap insulating layers and the first and second etch-stop layers are made of SiN, and

the first and second sidewall spacers are made of at least one of SiOC and SiOCN.

14. The method of claim 11 , wherein the first and second protective layers are made of at least one of aluminum nitride, aluminum oxynitride, aluminum oxide, titanium oxide, zirconium oxide.

15. The method of claim 11 , wherein the recessing the first and second cap insulating layers and the first and second etch-stop layers is performed before the recessing the first and second sidewall spacers.

16. The method of claim 11 , further comprising, after the forming the first protective layer:

removing the first insulating layer disposed over the source/drain region, thereby forming a contact hole; and

filling the contact hole with a conductive material;

recessing the filled conductive material; and

forming a second insulating layer over the recessed conductive material,

wherein when forming the contact hole, the first and second cap insulating layers are not etched.

17. A method of manufacturing a semiconductor device, the method comprising:

forming a gate structure over a substrate, the gate structure including a gate electrode, a first cap insulating layer disposed over the gate electrode, first sidewall spacers disposed on opposing side faces of the gate electrode and the first cap insulating layer and second sidewall spacers disposed on the first sidewall spacers, the gate structure extending in a first direction and surrounded by a first insulating layer;

after the forming the gate structure, recessing the first cap insulating layer such that an uppermost portion of the recessed first cap insulating layer is located at a first level lower than an upper surface of the first insulating layer, recessing the second sidewall spacers to a second level lower than the upper surface of the first insulating layer, and recessing the first sidewall spacers to a third level lower than the upper surface of the first insulating layer, thereby forming a first recessed space; and

forming a first protective layer in the first recessed space,

wherein, in forming the first recessed space, the third level is different from at least one selected from the group consisting of the first level and the second level.

18. The method of claim 17 , wherein the third level is lower than the first level.

19. The method of claim 17 , wherein the third level is lower than the second level.

20. The method of claim 17 , wherein:

the recessing the first cap insulating layer and the second sidewall spacers, and recessing the first sidewall spacers includes a first recess dry etching and a second recess dry etching as a different etching process than the first recess etching process,

the first recess dry etching includes etching the cap insulating layer and the second sidewall spacers, and

the second recess dry etching includes partially etching the first sidewall spacers.

21. The method of claim 17 , wherein the third level is higher than an upper surface of the gate electrode.

22. The method of claim 1 , wherein:

an upper surface of the recessed first cap insulating layer is located at a level lower than an upper surface of the first insulating layer, and

upper surfaces of the recessed first sidewall spacers are located at a level higher than an upper surface of the first gate electrode.