IP Library › Granted Patent US 10,164,051
Granted Patent B2
US 10,164,051 · App. 14/942,657 · Granted Dec 25, 2018

Method of cutting metal gate

Inventor: Kai-Chieh Yang (Kaohsiung, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L29/66545H01L21/823431H01L21/823437H01L21/823468H01L21/823481
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Quick Facts
Patent No.
US 10,164,051
App. No.
14/942,657
Granted
Dec 25, 2018
Kind
B2
Abstract

A method for fabricating a semiconductor device includes forming a first fin and a second fin on a substrate, forming a first metal-gate line over a first and a second gate regions, applying a first line-cut to separate the first metal-gate line into a first sub-metal gate line and a second sub-metal gate line and forming a second metal-gate line over the first sub-metal gate line and the second sub-metal gate line, applying a second line-cut to separate the second metal-gate line into a third sub-metal gate line and a fourth sub-metal gate line such that a gap is formed between the third sub-metal gate line and the fourth sub-metal gate line and forming an isolation region within the gap.

Claims (98)

1. A method comprising:

forming a first fin and a second fin on a substrate, the first fin having a first gate region and the second fin having a second gate region, the first fin being parallel to and spaced apart from the second fin by an isolation feature;

forming a first metal-gate line traversing the first and second fins over the first and second gate regions, wherein the first metal-gate line extends lengthwise from the first fin to the second fin, wherein the forming of the first metal-gate line over the first and second gate regions includes forming a first metal layer over the first and second gate regions;

forming a first sacrificial layer over the first metal layer;

recessing a portion of the first sacrificial layer to expose a portion of the first metal layer, resulting in a recessed first sacrificial layer; and

recessing the portion of the first metal layer, resulting in a recessed first metal layer;

applying a first line-cut to separate the first metal-gate line into a first sub-metal gate line and a second sub-metal gate line, wherein the applying of the first line-cut to separate the first metal-gate line into the first sub-metal gate line and the second sub-metal gate line includes:

forming a second sacrificial layer over the recessed first metal layer;

forming a patterned hard mask over the second sacrificial layer, wherein the patterned hard mask defines an opening;

etching the second sacrificial layer through the opening; and

etching the recessed first metal layer through the opening;

forming a second metal-gate line over the first sub-metal gate line and the second sub-metal gate line, wherein the second metal-gate line extends from the first fin to the second fin;

applying a second line-cut to separate the second metal-gate line into a third sub-metal gate line and a fourth sub-metal gate line such that a gap is formed between the third sub-metal gate line and the fourth sub-metal gate line; and

forming an isolation region within the gap.

2. The method of claim 1 , further comprising:

prior to the forming of the first metal-gate line over the first and second gate regions, forming a dummy gate stack over the first and second gate regions; and

forming an interlayer dielectric (ILD) layer over the substrate, including beside the dummy gate stack.

3. The method of claim 2 , wherein forming the first metal-gate line over the first and second gate regions includes:

prior to the forming of the first metal layer in the first and second gate regions, removing the dummy gate stack to expose a portion of the first gate region and a portion of the second gate region; and

forming a gate dielectric layer over the portions of the first and second gate regions.

4. The method of claim 1 , further comprising:

after the recessing of the portion of the first metal layer, removing the recessed first sacrificial layer.

5. The method of claim 1 , wherein the forming of the second metal-gate line over the first sub-metal gate line and the second sub-metal gate line includes:

forming a second metal layer over the first sub-metal gate line and the second sub-metal gate line, including over in the first line-cut;

forming a third sacrificial layer over the second metal layer;

recessing a portion of the third sacrificial layer to expose a portion of the second metal layer, resulting in a recessed third sacrificial layer;

recessing the portion of the second metal layer, resulting in a recessed second metal layer, wherein a surface of the recessed second metal layer is substantially coplanar with a surface of the recessed third sacrificial layer; and

removing the recessed third sacrificial layer.

6. The method of claim 5 , wherein the applying of the second line-cut to separate the second metal-gate line into the third sub-metal gate line and the fourth sub-metal gate line includes:

forming a dielectric layer over the recessed second metal layer;

forming a patterned hard mask over the dielectric layer, wherein the patterned hard mask defines an opening;

etching the dielectric layer through the opening; and

etching the recessed second metal layer through the opening.

7. The method of claim 6 , wherein the forming of the isolation region within the gap includes:

forming another dielectric layer in the gap; and

recessing the another dielectric layer.

8. A method comprising:

forming a first fin and a second fin on a substrate, the first fin having a first gate region and the second fin having a second gate region;

forming a first metal-gate line over the first and second gate regions, wherein the first metal-gate line extends from the first fin to the second fin;

forming a first sacrificial layer over the first metal-gate line;

forming a first patterned hard mask over the first sacrificial layer, wherein the first patterned hard mask defines a first opening;

etching the first sacrificial layer through the first opening;

etching the first metal-gate line through the first opening to form a first cut, wherein the first metal-gate line is separated into a first sub-metal gate line and a second sub-metal gate line by the first cut;

forming a second metal-gate line over the first sub-metal gate line, the second sub-metal gate line and the first cut, wherein the second metal-gate line extends from the first fin to the second fin;

forming a dielectric layer over the second metal-gate line;

forming a second patterned hard mask over the dielectric layer, wherein the second patterned hard mask defines a second opening;

etching the dielectric layer through the second opening; and

etching the second metal-gate line through the second opening to form a second cut, wherein the second metal-gate line is separated into a third sub-metal gate line and a fourth sub-metal gate line by the second cut.

9. The method of claim 8 , further comprising:

forming another dielectric layer in the first cut and the second cut; and

recessing the another dielectric layer to form an isolation region.

10. The method of claim 8 , further comprising:

prior to the forming of the first metal-gate line over the first and second gate regions, forming a dummy gate stack over the first and second gate regions; and

forming an interlayer dielectric (ILD) layer over the dummy gate stack and first source/drain features.

11. The method of claim 10 , wherein the forming of the first metal-gate line over the first and second gate regions includes:

removing the dummy gate stack to expose a portion of the first and second gate regions;

depositing a gate dielectric layer over the portions of the first and second gate regions; and

depositing a first metal layer over the gate dielectric layer in the first and second gate regions.

12. The method of claim 11 , further comprising:

depositing a sacrificial layer over the first metal layer;

recessing a portion of the sacrificial layer to expose a portion of the first metal layer, resulting in a recessed sacrificial layer;

recessing the portion of the first metal layer, resulting in a recessed first metal layer, wherein a surface of the recessed first metal layer is substantially coplanar with a surface of the recessed sacrificial layer; and

removing the recessed sacrificial layer.

13. The method of claim 12 , wherein the recessing of the portion of the sacrificial layer to expose the portion of the first metal layer includes recessing the sacrificial layer without substantially etching the first metal layer.

14. The method of claim 12 , wherein the recessing of the portion of the first metal layer includes recessing the first metal layer without substantially etching the sacrificial layer.

15. The method of claim 12 , wherein the forming of the second metal-gate line over the first sub-metal gate line and the second sub-metal gate line includes:

depositing a second metal layer over the first sub-metal gate line and the second sub-metal gate line;

depositing a sacrificial layer over the second metal layer;

recessing a portion of the sacrificial layer to expose a portion of the second metal layer;

recessing the portion of the second metal layer, resulting in a recessed second metal layer, wherein a surface of the recessed second metal layer is substantially coplanar with a surface of the recessed sacrificial layer; and

removing the recessed sacrificial layer.

16. A method comprising:

forming a plurality of fins on a substrate, each of the fins having a gate region;

forming dummy gate stack in each gate region;

forming sidewall spacers along sidewalls of each dummy gate stack;

forming an interlayer dielectric (ILD) layer over the substrate, including beside the dummy gate stacks;

removing the dummy gate stacks to expose portions of the fins;

forming a first metal layer over the portions of the fins, wherein the first metal layer forms a first metal-gate line;

forming a first line-cut to cut the first metal-gate line into first sub-metal-gate lines, including:

forming a first sacrificial layer over the first metal-gate line,

forming a first patterned hard mask over the first sacrificial layer, wherein the first patterned hard mask has a first opening such that a portion of the first metal layer aligned within the first opening, and

etching the first sacrificial layer through the first opening;

forming a second metal layer over first sub-metal-gate lines, including over the first line-cut, wherein the second metal layer forms a second metal-gate line;

forming a second line-cut to cut the second metal-gate line into second sub-metal-gate lines; and

forming an isolation region within the first and second line-cuts.

17. The method of claim 16 , wherein the forming of the first line-cut to cut the first metal-gate line into first sub-metal-gate lines includes:

after the etching of the first sacrificial layer through the first opening, etching the first metal-gate line through the first opening.

18. The method of claim 16 , wherein the forming of the second line-cut to cut the second metal-gate line into second sub-metal-gate lines includes:

forming a dielectric layer over the second metal-gate line;

forming a second patterned hard mask over the dielectric layer, wherein the second patterned hard mask has a second opening such that the first line-cut is aligned within the second opening;

etching the dielectric layer through the second opening; and

etching the second metal layer through the second opening.

19. The method of claim 18 , wherein the forming of the isolation region within the first and second line-cuts includes:

forming another dielectric layer in the first line-cut and the second line-cut; and

recessing the another dielectric layer.

20. The method of claim 1 , wherein the isolation feature is a dielectric isolation feature disposed within the substrate,

wherein the forming of the first metal layer over the first and second gate regions includes forming the first metal layer over the dielectric isolation feature disposed within the substrate, and

wherein the applying of the first line-cut to separate the first metal-gate line into a first sub-metal gate line and a second sub-metal gate line includes removing a portion of first metal layer to expose the dielectric isolation feature.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2016
From: YANG, KAI-CHIEH
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 039192/0281 →
Continuity (1)
Related Publication 20170141210A1 · May 18, 2017