Semiconductor device and method for fabricating the same
A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.
1. A semiconductor device, comprising:
an interfacial layer on a substrate;
a gate structure on the interfacial layer, wherein the gate structure comprises a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different, wherein the horizontal direction width of the patterned high-k dielectric layer is taken in a horizontal direction from the substrate;
a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer; and
a second spacer on the sidewalls of the first spacer and the interfacial layer, wherein a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer and a tip of the first spacer, a tip of the second spacer, and a top surface of the gate structure are coplanar.
2. The semiconductor device of claim 1 , wherein the interfacial layer comprises silicon dioxide.
3. The semiconductor device of claim 1 , wherein the gate structure comprises the patterned high-k dielectric layer, a patterned bottom barrier metal (BBM) layer on the patterned high-k dielectric layer, a patterned silicon layer on the patterned BBM layer, and a patterned hard mask on the patterned silicon layer.
4. The semiconductor device of claim 3 , wherein the patterned BBM layer comprises TiN.
5. The semiconductor device of claim 3 , wherein the patterned silicon layer comprises amorphous silicon or polysilicon.
6. The semiconductor device of claim 1 , wherein the first spacer comprises silicon dioxide or silicon nitride.
7. The semiconductor device of claim 1 , wherein the horizontal direction width of the interfacial layer is wider than a horizontal direction width of the gate structure.
8. The semiconductor device of claim 1 , wherein an edge of the interfacial layer is aligned with an edge of the first spacer.
9. The semiconductor device of claim 1 , further comprising a contact etch stop layer (CESL) around the second spacer, wherein a bottom surface of the CESL is lower than the planar bottom surface of the first spacer.