Semiconductor structure with protection layer

1. A method for forming a semiconductor structure, comprising:

forming a first protection layer having a first portion, a second portion and a third portion over a first portion of a substrate;

forming a first dummy gate structure over the first portion of the first protection layer;

forming a first spacer on a sidewall of the first dummy gate structure and over the second portion of the first protection layer;

removing the third portion of the first protection layer which is exposed by the first dummy gate structure and the first spacer;

replacing the first portion of the first protection layer and the first dummy gate structure by a first gate dielectric layer, wherein a thickness of the first protection layer is greater than a thickness of the first gate dielectric layer;

replacing the first gate dielectric layer by an interfacial layer, wherein the thickness of the first gate dielectric layer is greater than a thickness of the interfacial layer; and

forming a first gate electrode layer over the interfacial layer.

2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the thickness of the first protection layer is in a range from about 20 Å to about 100 Å.

3. The method for forming a semiconductor structure as claimed in claim 2 , wherein a difference between the thickness of the first protection layer and the thickness of the first gate dielectric layer is in a range of about 5 Å to about 80 Å.

4. The method for forming a semiconductor structure as claimed in claim 1 , wherein the first protection layer and the first gate dielectric layer are made of a same material.

5. The method for forming a semiconductor structure as claimed in claim 4 , wherein the second portion of the first protection layer is in direct contact with the first gate dielectric layer.

6. The method for forming a semiconductor structure as claimed in claim 1 , further comprising:

forming a fin structure over the substrate;

forming an isolation structure around the fin structure,

wherein the first protection layer is formed over the fin structure and extends over the isolation structure.

7. The method for forming a semiconductor structure as claimed in claim 1 , further comprising:

forming a second protection layer having a first portion, a second portion and a third portion over a second portion of the substrate;

forming a second dummy gate structure over the first portion of the second protection layer;

forming a second spacer on a sidewall of the second dummy gate structure and over the second portion of the second protection layer;

removing the third portion of the second protection layer which is exposed by the second dummy gate structure and the second spacer; and

replacing the first portion of the second protection layer and the second dummy gate structure by a second gate dielectric layer and a second gate electrode layer, wherein the first gate dielectric layer and the second gate dielectric layer are formed by a single process.

8. A method for forming a semiconductor structure, comprising:

forming a first protection layer over a first region of a substrate and a second protection layer over a second region of the substrate;

forming a first dummy gate structure over the first protection layer and a second dummy gate structure over the second protection layer;

forming first spacers over sidewalls of the first dummy gate structure and second spacers over sidewalls of the second dummy gate structure;

removing the first dummy gate structure to form a first trench and removing the second dummy gate structure to form a second trench;

removing the first protection layer exposed by the first trench and the second protection layer exposed by the second trench;

forming a first gate dielectric layer in the first trench and a second gate dielectric layer in the second trench, wherein a thickness of the first protection layer is greater than a thickness of the first gate dielectric layer;

removing the first gate dielectric layer to expose a portion of a top surface of the substrate;

forming an interfacial layer over the portion of the top surface of the substrate exposed by the first trench;

forming a first gate structure over the interfacial layer; and

forming a second gate structure over the second gate dielectric layer.

9. The method for forming a semiconductor structure as claimed in claim 8 , wherein the first gate dielectric layer and the second gate dielectric layer are formed by performing a same deposition process.

10. The method for forming a semiconductor structure as claimed in claim 8 , wherein an interface between the first protection layer and the first spacer is at a higher position than a top surface of the interfacial layer.

11. The method for forming a semiconductor structure as claimed in claim 8 , wherein the second protection layer is thicker than the second gate dielectric layer.

12. The method for forming a semiconductor structure as claimed in claim 8 , wherein the first region is a core region and the second region is an input/output region.

13. The method for forming a semiconductor structure as claimed in claim 8 , wherein the first protection layer is thicker than the second gate dielectric layer, and the second gate dielectric layer is thicker than the interfacial layer.

14. The method for forming a semiconductor structure as claimed in claim 8 , wherein the first protection layer, the second protection layer and the second gate dielectric layer are made of a same material.

15. The method for forming a semiconductor structure as claimed in claim 14 , wherein the first protection layer and the second protection layer are formed by performing a same deposition process.

16. A method for forming a semiconductor structure, comprising:

forming a protection layer over a fin structure of a substrate;

forming a dummy gate structure across the fin structure and over the protection layer;

forming a spacer on a sidewall of the dummy gate structure and over the protection layer;

removing the dummy gate structure to form a trench exposing a portion of the protection layer;

removing the portion of the protection layer exposed by the trench, wherein a width of the protection layer is substantially the same as a width of the spacer after removing the portion of the protection layer;

forming a gate dielectric layer in the trench, wherein the protection layer and the gate dielectric layer are made of a same material and a thickness of the protection layer is greater than a thickness of the gate dielectric layer;

removing the gate dielectric layer to expose a portion of a top surface of the fin structure; and

forming an interfacial layer over the portion of the top surface of the fin structure exposed by the trench, wherein the thickness of the protection layer is greater than a thickness of the interfacial layer.

17. The method for forming a semiconductor structure as claimed in claim 16 , wherein the thickness of the protection layer is in a range from about 20 Å to about 100 Å.

18. The method for forming a semiconductor structure as claimed in claim 16 , wherein the protection layer is an oxide layer.

19. The method for forming a semiconductor structure as claimed in claim 16 , wherein the portion of the protection layer is in direct contact with the gate dielectric layer.

20. The method for forming a semiconductor structure as claimed in claim 16 , further comprising:

forming a gate electrode layer over the gate dielectric layer.