Semiconductor device including memory and logic circuit having FETs with ferroelectric layer and manufacturing methods thereof
A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.
1. A semiconductor device, comprising:
a memory circuit including:
a word line;
a bit line;
a common line; and
a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line; and
a logic circuit including:
a logic transistor having a gate, a drain and a source, wherein:
the gate of the memory transistor has a gate electrode layer formed on a gate dielectric layer, the gate dielectric layer including a first insulating layer and a first ferroelectric (FE) material layer, and
the gate of the logic transistor has a gate electrode layer formed on a gate dielectric layer, the gate dielectric layer including a second insulating layer and a second FE material layer,
wherein a thickness of the first insulating layer is different from a thickness of the second insulating layer.
2. The semiconductor device of claim 1 , wherein:
the first FE material layer and the second FE material layer are made of a same FE material and have a same thickness.
3. The semiconductor device of claim 1 , wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer.
4. The semiconductor device of claim 1 , wherein a thickness of the first insulating layer is smaller than a thickness of the second insulating layer.
5. The semiconductor device of claim 1 , wherein:
the same FE material is HfO 2 doped with Si.
6. The semiconductor device of claim 1 , wherein the logic circuit includes a CMOS inverter, and the FET is one of two FETs of the CMOS inverter.
7. The semiconductor device of claim 1 , wherein the logic circuit is one or more of a word deriver and a sense amplifier of the memory circuit.
8. The semiconductor device of claim 2 , wherein:
the same FE material is one of PGO, PZT, SBT, SBO, SBTO, SBTN, STO, BTO, BLT, LNO, YMnO 3 , ZrO 2 , zirconium silicate, ZrAlSiO, HfO 2 , hafnium silicate, HfAlO, LaAlO, lanthanum oxide, HfO 2 doped with Si and Ta 2 O 5 .
9. The semiconductor device of claim 2 , wherein the same thickness is in a range from 1 nm to 300 nm.
10. The semiconductor device of claim 2 , wherein the first and second insulating layers are made of one or more layers of SiO 2 , SiN and SiON.
11. The semiconductor device of claim 2 , wherein the gate electrode layer of the memory transistor and the gate electrode layer of the FET are made of polysilicon.
12. The semiconductor device of claim 2 , wherein the thickness of the first and second FE material layer is greater than the thickness of the first insulating layer and the thickness of the second insulating layer.
13. The semiconductor device of claim 3 , wherein the thickness of the first insulating layer is in a range from 3 nm to 9 nm and the thickness of the second insulating layer is in a range from 1 nm to 3 nm.
14. The semiconductor device of claim 4 , wherein the thickness of the first insulating layer is in a range from 1 nm to 3 nm and the thickness of the second insulating layer is in a range from 3 nm to 9 nm.
15. A semiconductor device, comprising:
a memory circuit including:
a word line;
a bit line;
a common line; and
a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line; and
a logic circuit including:
a logic transistor having a gate, a drain and a source, wherein:
the gate of the memory transistor has a gate electrode layer formed on a gate dielectric layer, the gate dielectric layer including a first insulating layer and a first ferroelectric (FE) material layer,
the gate of the logic transistor has a gate electrode layer formed on a gate dielectric layer, the gate dielectric layer including a second insulating layer and a second FE material layer, and
wherein a thickness of the gate electrode layer of the memory transistor is different from a thickness of the gate electrode layer of the logic transistor.
16. A method for manufacturing a semiconductor device including a memory circuit and a logic circuit, the method comprising:
forming an isolation region in a substrate to define a memory area and a logic area;
forming an insulating layer over the memory area and the logic area;
reducing a thickness of the insulating layer of the memory area;
forming a ferroelectric (FE) material layer over the reduced thickness insulating layer of the memory area and the insulating layer of the logic area;
forming a conductive material layer over the FE material layer;
patterning the conductive material layer and the FE material layer;
forming sidewall spacer layers; and
forming a metal gate structure by using a gate replacement technology, thereby forming a memory gate structure in the memory area and a logic gate structure in the logic area.
17. The method of claim 16 , wherein:
the FE material layer is made of HfO 2 doped with Si, and
the insulating layer is made of SiO 2 .
18. The method of claim 16 , wherein after the reducing a thickness of the insulating layer of the memory area, the thickness of the insulating layer of the logic area is in a range from 3 nm to 9 nm and the thickness of the insulating layer of the memory area is in a range from 1 nm to 3 nm.
19. A method for manufacturing a semiconductor device including a memory circuit and a logic circuit, the method comprising:
forming an isolation region in a substrate to define a memory area and a logic area;
forming an insulating layer over the memory area and the logic area;
reducing a thickness of the insulating layer of the logic area;
forming a ferroelectric (FE) material layer over the insulating layer of the memory area and the reduced thickness insulating layer of the logic area;
forming a conductive material layer over the FE material layer;
patterning the conductive material layer and the FE material layer;
forming sidewall spacer layers; and
forming a metal gate structure by using a gate replacement technology, thereby forming a memory gate structure in the memory area and a logic gate structure in the logic area.
20. The method of claim 19 , wherein:
the FE material layer is made of HfO 2 doped with Si, and the insulating layer is made of SiO 2 .