IP Library Granted Patent US 10,164,738
Granted Patent B2
US 10,164,738 · App. 15/377,707 · Granted Dec 25, 2018

Interlacing method for high throughput forward error correction

Inventors: Thomas Joseph Richardson (South Orange, NJ); Vincent Abayomi Loncke (Piscataway, NJ)
Assignee: QUALCOMM Incorporated
H04L1/0061H03M13/27H04L1/0042H04L1/0071H04L1/0041H04L1/0065
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Quick Facts
Patent No.
US 10,164,738
App. No.
15/377,707
Granted
Dec 25, 2018
Kind
B2
Abstract

Encoders, decoders and methods of encoding and decoding data can comprise receiving source symbols in a first sequence, storing the source symbols to a first memory in a second sequence, wherein the first sequence is a first interlacing relative to the second sequence, determining if the memory contains all source symbols of a codeword, wherein the source symbols of a codeword are the symbols used to generate repair symbols for that codeword, generating repair symbols for the codeword, storing the repair symbols to a second memory in a third sequence, interlacing the repair symbols and the source symbols into an output stream as a stream of encoded symbols, wherein the repair symbols appear in the output stream in a fourth sequence, wherein the fourth sequence is a second interlacing relative to the third sequence, and outputting the stream of encoded symbols.

Claims (35)

1. A method of encoding data for transmission comprising:

receiving source symbols in a first sequence;

storing the source symbols to a first memory in a second sequence, wherein the first sequence is a first interlacing relative to the second sequence;

determining if the first memory contains all source symbols of a codeword, wherein the source symbols of a codeword are the symbols used to generate repair symbols for that codeword;

generating repair symbols for the codeword;

storing the repair symbols to a second memory in a third sequence;

interlacing the repair symbols and the source symbols into an output stream as a stream of encoded symbols, wherein the repair symbols appear in the output stream in a fourth sequence, wherein the fourth sequence is a second interlacing relative to the third sequence; and

outputting the stream of encoded symbols.

2. The method of claim 1 , further comprising:

receiving additional source symbols in the first sequence, the additional source symbols comprising a plurality of additional codewords;

storing the additional source symbols of the plurality of additional codewords in the first memory in the second sequence;

determining which of the additional codewords are complete codewords in the first memory;

for each of the complete codewords, generating repair symbols;

storing the repair symbols for each of the complete codewords to the second memory in the third sequence; and

interlacing the repair symbols and the source symbols for each of the complete codewords into the output stream as the stream of encoded symbols prior to the outputting of the stream of encoded symbols.

3. The method of claim 1 , wherein the first interlacing and the second interlacing are equal.

4. The method of claim 1 , wherein the first interlacing and the second interlacing are determined from a target line rate, a specified protection period, and a specified symbol size.

5. The method of claim 1 , further comprising:

generating an encoding schedule in advance of receiving the source symbols; and

allocating codewords in the encoding schedule to stagger completion times of the codewords, wherein a completion time of a given codeword is a time at which a decoder obtains, or is scheduled to obtain, a last symbol of the given codeword.

6. The method of claim 1 , wherein the first memory and the second memory are each distinct memory locations in one common memory structure.

7. An encoder for encoding data for transmission comprising:

an input for receiving source symbols in a first sequence;

a first memory having storage for the source symbols corresponding to a codeword, wherein the source symbols corresponding to the codeword are symbols used to generate repair symbols for the codeword;

logic for storing the source symbols of the codeword to the first memory in a second sequence, wherein the first sequence is a first interlacing relative to the second sequence;

a repair encoder for generating repair symbols for the source symbols of the codeword;

a second memory having storage for storing the repair symbols in a third sequence;

an interlacer that interlaces the repair symbols and the source symbols into an output stream as a stream of encoded symbols, wherein the repair symbols appear in the output stream in a fourth sequence, wherein the fourth sequence is a second interlacing relative to the third sequence; and

an output for outputting the stream of encoded symbols.

8. The encoder of claim 7 , further comprising storage in memory for a plurality of additional source symbols in the first sequence, the additional source symbols comprising a plurality of additional codewords and storage in memory for the repair symbols for each of the plurality of additional codewords in the third sequence.

9. The encoder of claim 7 , wherein the first interlacing and the second interlacing are equal.

10. The encoder of claim 7 , wherein the first interlacing and the second interlacing are determined from a target line rate, a specified protection period, and a specified symbol size.

11. The encoder of claim 7 , further comprising:

storage for an encoding schedule generated in advance of receiving the source symbols, wherein codewords in the encoding schedule have staggered completion times of the codewords, wherein a completion time of a given codeword is a time at which a decoder obtains, or is scheduled to obtain, a last symbol of the given codeword.

12. The encoder of claim 7 , wherein the first memory and the second memory are each distinct memory locations in one common memory structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2016
From: RICHARDSON, THOMAS JOSEPH; LONCKE, VINCENT ABAYOMI
To: QUALCOMM INCORPORATED
Reel/Frame 040727/0263 →
Continuity (2)
Provisional Application 62268185 · Dec 16, 2015
Related Publication 20170180079A1 · Jun 22, 2017