IP Library › Granted Patent US 10,164,807
Granted Patent B2
US 10,164,807 · App. 15/481,038 · Granted Dec 25, 2018

Receiver circuits

Inventors: Muhammed Bolatkale (Eindhoven, NL); Lucien Johannes Breems (Eindhoven, NL)
Assignee: NXP B.V.
H04L25/08H03M1/001H03M1/1009H04B1/109H04B1/123H04B1/0007
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Quick Facts
Patent No.
US 10,164,807
App. No.
15/481,038
Granted
Dec 25, 2018
Kind
B2
Abstract

A receiver circuit comprising: an input terminal configured to receive an input-signal; a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal; a feedforward-DAC configured to provide a feedforward-analog-signal based on the feedforward-digital-signal; a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analog-signal and the input-signal; an error-LNA configured to provide an amplified-error-signal based on the error-signal; an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal; a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal.

Claims (45)

1. A receiver circuit comprising:

an input terminal configured to receive an input-signal;

a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal;

a feedforward-DAC configured to provide a feedforward-analogue-signal based on the feedforward-digital-signal;

a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analogue-signal and the input-signal;

a low pass filter between the feedforward-DAC and the feedforward-subtractor;

an error-LNA configured to provide an amplified-error-signal based on the error-signal;

an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal;

a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and

an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal, wherein the mixer comprises an error-mixer configured to down-convert the error-signal in order to provide a down-converted-error-signal, wherein the error-LNA is configured to provide the amplified-error-signal based on the down-converted-error-signal.

2. The receiver circuit of claim 1 , wherein the mixer comprises an input-mixer configured to down-convert the input-signal in order to provide a down-converted-input-signal, wherein the feedforward-ADC is configured to provide the feedforward-digital-signal based on the down-converted-input-signal, and wherein the feedforward-subtractor is configured to provide the error-signal based on the difference between the feedforward-analogue-signal and the down-converted-input-signal.

3. The receiver circuit of claim, 1 wherein the mixer comprises a feedforward-input-mixer configured to down-convert the input-signal in order to provide a down-converted-input-signal, wherein the feedforward-ADC is configured to provide the feedforward-digital-signal based on the down-converted-input-signal, the feedforward-subtractor is configured to provide the error-signal based on the difference between the feedforward-analogue-signal and the input-signal, and wherein the signal that is provided as an input to the feedforward-ADC is a down-converted version of the signal that is provided as an input to the feedforward-subtractor.

4. The receiver circuit of claim 1 , wherein the mixer comprises a feedforward-analogue-mixer configured to down-convert the feedforward-analogue-signal in order to provide a down-converted-feedforward-analogue-signal, wherein the feedforward-subtractor is configured to provide an error-signal based on the difference between the down-converted-feedforward-analogue-signal and the input-signal.

5. The receiver circuit of claim 1 , wherein the mixer comprises a feedforward-digital-mixer configured to down-convert the feedforward-digital-signal in order to provide a down-converted-feedforward-digital-signal, wherein the feedforward-DAC is configured to provide the feedforward-analogue-signal based on the down-converted-feedforward-digital-signal.

6. The receiver circuit of claim 1 , wherein the mixer comprises inherent aliasing characteristics of the feedforward-ADC and the feedforward-DAC.

7. The receiver circuit of claim 1 , wherein the feedforward-ADC comprises a wideband ADC and wherein the feedforward-DAC comprises a wideband DAC.

8. The receiver circuit of claim 1 , further comprising a delay-block configured to provide a delayed-input-signal based on the input-signal, and wherein the feedforward-subtractor is configured to provide the error-signal based on the difference between the feedforward-analogue-signal and the delayed-input-signal.

9. The receiver circuit of claim 1 , further comprising:

an interference-input terminal configured to receive an interference-input-signal representative of a transmitted-signal from a co-located transmitter; and

an interference-compensator configured to provide a compensated-input-signal based on the interference-input-signal and the input-signal, wherein the feedforward-ADC is configured to provide the feedforward-digital-signal based on the compensated-input-signal, and wherein the feedforward-subtractor is configured to provide the error-signal based on the difference between the feedforward-analogue-signal and the compensated-input-signal.

10. The receiver circuit of claim 9 , wherein the interference-compensator comprises an interference-cancellation-block configured to generate a modelled-interference-signal based on: (i) a model of a signal coupling path between transmitter and receiver antennas; and (ii) the interference-input-signal, and wherein the interference-compensator is configured to provide the compensated-input-signal based on the modelled-interference-input-signal and the input-signal.

11. The receiver circuit of claim 9 , wherein the interference-compensator is configured to be operated in accordance with an operating-state of the transmitter.

12. The receiver circuit of claim 1 , further comprising a digital-noise-shaper configured to generate a 1-bit noise-shaped-feedforward-signal based on the feedforward-digital-signal, and wherein the feedforward-DAC is configured to provide the feedforward-analogue-signal based on the noise-shaped-feedforward-signal.

13. The receiver circuit of claim 1 , further comprising a calibration-feedback-path configured to provide a calibration-error-signal based on the amplified-error-signal to the error-cancellation-block, and wherein the error-cancellation-block is configured to set component/operational parameters for one or more components in a signal path between the input terminal and the error-ADC.

14. The receiver circuit of claim 1 , wherein the feedforward-DAC comprises a multi-tap FIRDAC.

15. A receiver circuit comprising:

an input terminal configured to receive an input-signal;

a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal;

a feedforward-DAC configured to provide a feedforward-analogue-signal based on the feedforward-digital-signal;

a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analogue-signal and the input-signal;

an error-LNA configured to provide an amplified-error-signal based on the error-signal;

an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal;

a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and

an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal, wherein the mixer comprises an input-mixer configured to down-convert the input-signal in order to provide a down-converted-input-signal, wherein the feedforward-ADC is configured to provide the feedforward-digital-signal based on the down-converted-input-signal, and wherein the feedforward-subtractor is configured to provide the error-signal based on the difference between the feedforward-analogue-signal and the down-converted-input-signal.

16. A receiver circuit comprising:

an input terminal configured to receive an input-signal;

a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal;

a feedforward-DAC configured to provide a feedforward-analogue-signal based on the feedforward-digital-signal;

a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analogue-signal and the input-signal;

a low pass filter between the feedforward-DAC and the feedforward-subtractor;

an error-LNA configured to provide an amplified-error-signal based on the error-signal;

an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal;

a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and

an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal,

wherein the mixer comprises an input-mixer configured to down-convert the input-signal in order to provide a down-converted-input-signal, wherein the feedforward-ADC is configured to provide the feedforward-digital-signal based on the down-converted-input-signal, and wherein the feedforward-subtractor is configured to provide the error-signal based on the difference between the feedforward-analogue-signal and the down-converted-input-signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2017
From: BOLATKALE, MUHAMMED; BREEMS, LUCIEN JOHANNES
To: NXP B.V.
Reel/Frame 041888/0541 →
Priority Claims (1)
EP 16167566 · Apr 28, 2016 · regional
Continuity (1)
Related Publication 20170317860A1 · Nov 2, 2017