Semiconductor memory device with bit line contact structure and method of forming the same
The present invention provides a method of forming a semiconductor device. First, providing a substrate, and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.
1. A semiconductor structure, comprising:
a substrate, comprising a first active region and a plurality of second active regions;
a shallow trench isolation, disposed in the substrate and between the first active region and the second active regions;
a bit line contact opening, disposed in the first active region and the shallow trench isolation;
a bit line contact structure, disposed in the bit line contact opening and contacts the first active region; and
a spacer disposed in the bit line contact opening, wherein the spacer has a sidewall directly contacting one of the second active regions;
a mask layer disposed on the second active regions and exposing the bit line contact opening;
wherein the spacer extends beneath the mask layer to contact the first active region.
2. The semiconductor structure according to claim 1 , wherein the spacer is disposed above the shallow trench isolation.
3. The semiconductor structure according to claim 1 , further comprising a patterned mask layer, which is disposed on the first active region and exposing the bit line contact opening.
4. The semiconductor structure according to claim 3 , wherein the spacer has another sidewall disposed under the patterned mask layer.
5. The semiconductor structure according to claim 3 , wherein the spacer has another sidewall protrudes from the patterned mask layer.
6. The semiconductor structure according to claim 3 , wherein the spacer has another sidewall vertically aligns with a sidewall of the patterned mask layer.
7. The semiconductor structure according to claim 1 , wherein the bit line contact opening comprises a sidewall, and the sidewall extends to a same depth as a bottommost surface of the shallow trench isolation.