Contact resistance control in epitaxial structures of finFET
A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and etching back portions of the fin regions to form recessed fin regions. The method further includes forming a merged epitaxial region on the recessed fin regions and forming a capping layer on the merged epitaxial region using an etching gas and a deposition gas. The forming of the capping layer may include epitaxially growing a material of the capping layer faster along a first crystal direction of the capping layer than a second crystal direction of the capping layer by adjusting a ratio of a concentration of a first element in the etching gas to a concentration of a second element in the deposition gas, the first and second elements being different from each other, the first and second crystal directions being different from each other.
1. A semiconductor device, comprising:
fin regions on a substrate;
shallow trench isolation (STI) regions between the fin regions;
a replacement gate structure over the fin regions and the STI regions;
a merged epitaxial region; and
a capping layer, on the merged epitaxial region, with a top surface having a vertical dimension between a highest point and a lowest point less than about 5 nm.
2. The semiconductor device of claim 1 , wherein the capping layer is thicker along a [110] crystal direction of the capping layer than along a [001] or [111] crystal direction of the capping layer.
3. The semiconductor device of claim 1 , wherein a thickness of the capping layer ranges from about 2 nm to about 7 nm.
4. The semiconductor device of claim 1 , wherein the capping layer comprises an n-type epitaxial material.
5. The semiconductor device of claim 1 , wherein the capping layer comprises silicon doped phosphorous with a phosphorous dopant concentration between about 1×10 19 atoms/cm 3 and about 1×10 21 atoms/cm 3 .
6. The semiconductor device of claim 1 , wherein the merged epitaxial region comprises silicon doped phosphorous with a phosphorous dopant concentration between about 1×10 19 atoms/cm 3 and about 4×10 21 atoms/cm 3 .
7. The semiconductor device of claim 1 , wherein the capping layer comprises a silicon doped phosphorous epitaxial layer.
8. The semiconductor device of claim 1 , further comprising
an insulating void positioned under the merged epitaxial region.
9. A semiconductor structure, comprising:
fin regions on a substrate;
one or more replacement gate structures on the fin regions;
a merged epitaxial region on the fin regions; and
a capping layer, on the merged epitaxial region, with a top surface having a vertical dimension between a highest point and a lowest point less than about 5 nm and a dopant concentration between about 1×10 19 atoms/cm 3 and about 1×10 21 atoms/cm 3 .
10. The semiconductor structure of claim 9 , wherein the dopant concentration comprises n-type dopants.
11. The semiconductor structure of claim 9 , wherein the dopant concentration comprises phosphorous.
12. The semiconductor structure of claim 9 , wherein the capping layer comprises an epitaxially grown phosphorous doped silicon.
13. The semiconductor device of claim 9 , wherein a thickness of the capping layer ranges from about 2 nm to about 7 nm.
14. The semiconductor device of claim 9 , wherein a ratio of a first vertical dimension between lowest points on the capping layer and the merged epitaxial region to a second vertical dimension between highest points on the capping layer and the merged epitaxial region is between 1 and 5.
15. The semiconductor device of claim 9 , wherein the capping layer is thicker on a first crystal direction of the capping layer than on a second crystal direction of the capping layer, the first crystal direction being different from the second crystal direction.
16. A semiconductor structure, comprising:
recessed fin regions on a substrate;
one or more replacement gate structures between the recessed fin regions;
a merged epitaxial region, on the recessed fin regions, with a non-planar top surface; and
a capping layer, on the merged epitaxial region, with a substantially planar top surface, wherein a ratio of a first vertical dimension between lowest points of the capping layer and the merged epitaxial region to a second vertical dimension between highest points of the capping layer and the merged epitaxial region is between 1 and 5.
17. The semiconductor structure of claim 16 , wherein the capping layer comprises phosphorous doped silicon with a phosphorous dopant concentration between about 1×10 19 atoms/cm 3 and about 1×10 21 atoms/cm 3 .
18. The semiconductor structure of claim 16 , wherein the capping layer and the merged epitaxial region comprise silicon doped phosphorous.
19. The semiconductor structure of claim 16 , wherein a thickness of the capping layer ranges from about 2 nm to about 7 nm.
20. The semiconductor structure of claim 16 , wherein a vertical distance between a highest point and a lowest point of the capping layer on the substantially planar top surface is between about 3 nm and about 5 nm.