Memory circuits and routing of conductive layers thereof
View Patent ↗A memory circuit memory circuit comprises at least one memory cell for storing a datum. The memory cell is coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line. A first conductive layer comprising a first landing pad and a second landing pad is arranged at a first level. A second conductive layer is coupled to the first conductive layer and arranged at a second level different from the first level. The second conductive layer is routed to define the first voltage line and the second voltage line. A third conductive layer is coupled to the second conductive layer and arranged at a third level different from the first level and the second level. The third conductive layer is routed to define the word line.
1. A memory circuit, comprising:
at least one memory cell for storing a datum, the memory cell being coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line;
a first conductive layer arranged at a first level, the first conductive layer comprising a first landing pad and a second landing pad, the first landing pad forming a landing site formed in the first conductive layer and on which a via lands, the via connecting the first conductive layer to a second conductive layer;
the second conductive layer coupled to the first conductive layer and arranged at a second level different from and over the first level, the second conductive layer being routed to define the first voltage line and the second voltage line, the first voltage line and the second voltage line extending in a first direction, wherein the first voltage line and the second voltage line are located within the second conductive layer; and
a third conductive layer coupled to the second conductive layer and arranged at a third level different from the first level and the second level, the third level over the second level, the third conductive layer being routed to define the word line, the word line extending in a second direction perpendicular to the first direction, wherein the bit line is located within the first conductive layer adjacent to the first landing pad, wherein the bit line in the first conductive layer extends past a periphery of the at least one memory cell in the first direction, wherein the bit line bar is located within the first conductive layer adjacent to the second landing pad, and wherein the bit line bar in the first conductive layer extends past the periphery of the at least one memory cell in the first direction.
2. The memory circuit of claim 1 , wherein, in a layout view, the bit line or the bit line bar is interposed between the first voltage line and the second voltage line.
3. The memory circuit of claim 1 , wherein the first voltage line is a V dd line and the second voltage line is a V ss line, and the word line is substantially orthogonal to the V ss line.
4. The memory circuit of claim 1 , wherein a first width of the third conductive layer for the word line within the memory cell is 50% or more of a second width of a short side of the memory cell.
5. The memory circuit of claim 1 , wherein
the first conductive layer defines electrical connections within the memory cell.
6. The memory circuit of claim 1 , wherein a length of a long side of the memory cell is at least 2.5 times greater than a width of a short side of the memory cell.
7. The memory circuit of claim 1 , wherein a length of the word line is at least 2.5 times greater than a length of the bit line.
8. A memory circuit, comprising:
at least one memory cell for storing a datum, the memory cell being coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line;
a first conductive layer arranged at a first level over a semiconductor substrate, the first conductive layer comprising a first landing pad and a second landing pad;
a second conductive layer coupled to the first conductive layer and arranged at a second level different from and over the first level, the second conductive layer being routed to define the first voltage line and the second voltage line, the first voltage line and the second voltage line extending in a first direction, wherein the first voltage line and the second voltage line are arranged within the second conductive layer; and
a third conductive layer coupled to the second conductive layer and arranged over the second conductive layer, the third conductive layer being routed to define the word line, the word line extending in a second direction perpendicular to the first direction, wherein the bit line is arranged within the first conductive layer adjacent to the first landing pad, and the bit line bar is arranged within the first conductive layer adjacent to the second landing pad, wherein the bit line and bit line bar extend in the first direction, and wherein the bit line and the bit line bar in the first conductive layer extend beyond a perimeter of the at least one memory cell.
9. The memory circuit of claim 8 , in a layout view, the bit line or the bit line bar is interposed between the first voltage line and the second voltage line.
10. The memory circuit of claim 8 , wherein the first voltage line is a V dd line and the second voltage line is a V ss line, and the word line is substantially orthogonal to the V ss line.
11. The memory circuit of claim 8 , wherein a first width of the third conductive layer for the word line within the memory cell is 50% or more of a second width of a short side of the memory cell.
12. The memory circuit of claim 8 , wherein the first conductive layer defines electrical connections within the memory cell.
13. The memory circuit of claim 8 , wherein a length of a long side of the memory cell is at least 2.5 times greater than a width of a short side of the memory cell.
14. The memory circuit of claim 8 , wherein a length of the word line is at least 2.5 times greater than a length of the bit line.
15. A memory circuit, comprising:
at least one memory cell for storing a datum, the memory cell being coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line;
a first layer defining electrical connections within the memory cell, the first layer comprising a first landing pad and a second landing pad, the first landing pad and the second landing pad defining respective landing sites for respective vias connecting the first layer and a second layer, the second layer over the first layer; and
the second layer being routed to define the first voltage line, the second layer comprising a third landing pad and a fourth landing pad, the third landing pad and fourth landing pad forming respective landing sites for respective vias connecting the second layer and a third layer, the third layer coupled to and over the second layer, the third layer being routed for the word line, wherein the bit line is disposed adjacent to the first landing pad, wherein the bit line bar is disposed adjacent to the second landing pad, wherein the bit line and the bit line bar are within the first layer, and wherein portions of the bit line and the bit line bar in the first layer extend outside a boundary of the at least one memory cell in the first layer.
16. The memory circuit of claim 15 , wherein the first layer is routed for the bit line and the bit line bar.
17. The memory circuit of claim 16 , wherein the second layer is over the first layer.
18. The memory circuit of claim 15 , wherein the second layer is routed for the first voltage line and the second voltage line.
19. The memory circuit of claim 15 , wherein the first voltage line is a Vdd line, the second voltage line is a Vss line, and the word line is substantially orthogonal to the Vss line.
20. The memory circuit of claim 15 , wherein the third layer is free from including the bit line, the bit line bar, the first voltage line, and the second voltage line within the memory cell.
21. The memory circuit of claim 1 , wherein a first width of the word line is greater than a third width of the first voltage line and a fourth width of the second voltage line.