Voltage balanced stacked clamp
Embodiments of the present invention provide systems and methods for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.
1. An apparatus for balancing voltages, comprising:
a voltage supply pin operatively connected to a voltage divider, wherein the voltage supply pin supplies a total voltage to the voltage divider;
a stacked circuit operatively connected to the voltage divider, wherein the stacked circuit comprises a first layer and a second layer, wherein the first layer is not coupled to the second layer, and the voltage divider distributes the total voltage as to the stacked circuit;
a voltage grounder operatively connected to the voltage divider and wherein the first layer and the second layer comprise:
a group of inverters within the first layer operatively connected to a first n-type channel field effect transistor (NFET), wherein the group of inverters within the first layer comprise:
a first inverter, a second inverter, and a third inverter, wherein
the first inverter connects the voltage divider to the second inverter, the second inverter connects to the third inverter, and wherein the third inverter connects to the first n-type channel field effect transistor (NFET); and
a group of inverters within the second layer operatively connected to a second n-type channel field effect transistor (NFET), wherein the group of inverters within the second layer comprise:
a first inverter, a second inverter, and a third inverter, wherein
the first inverter connects the voltage divider to the second inverter, the second inverter connects to the third inverter, and wherein the third inverter connects to the second n-type channel field effect transistor (NFET); and
a third node, wherein the third node is point (principal nodes or junctions) coupled to a first p-type field effect transistor (PFET) at a gate terminal of the first PFET, the second inverter, and the third inverter of the first layer.
2. The apparatus of claim 1 , wherein the voltage divider, comprises:
a first set of components operatively connected to the first layer, wherein the first set of components transfers a first voltage of the total voltage, from the voltage supply pin to the first layer; and
a second set of component operatively connected to the second layer, wherein the second set of component transfers a second voltage of the total voltage, from the voltage supply pin to the second layer.
3. The apparatus of claim 2 , further comprising:
a first capacitor operatively connected to the first set of components in the voltage divider at a first node;
a first resistor operatively connected to the second set of components in the voltage divider at a second node;
a second resistor operatively connected to the first capacitor; and
a second capacitor operatively connected to the first resistor.
4. The apparatus of claim 2 , wherein:
the first voltage is greater than half of the total voltage; and
the second voltage is less than or equal to half of the total voltage.
5. The apparatus of claim 4 , further comprising:
a fourth node operatively connected to a third inverter of the first layer, wherein the fourth node receives the first voltage; and
a fifth node operatively connected to a third inverter of the second layer, wherein the fifth node receives the second voltage.
6. The apparatus of claim 3 , further comprising:
a decoupling resistor, wherein the decoupling resistor operatively connects to a supply node of the first inverter of second layer and the voltage divider.
7. The apparatus of claim 3 , further comprising:
the third inverter of the first layer is operatively connected to the voltage divider.