Compound semiconductor devices having buried resistors formed in buffer layer
Structures and methods are provided for fabricating a semiconductor device (e.g., III-V compound semiconductor device) having buried resistors formed within a buffer layer of the semiconductor device. For instance, a semiconductor device includes a buffer layer disposed on a substrate, a channel layer disposed on the buffer layer, and a buried resistor disposed within the buffer layer. The buffer and channel layers may be formed of compound semiconductor materials such as III-V compound semiconductor materials. Utilizing the buffer layer of a compound semiconductor structure to form buried resistors provides a space-efficient design with increased integration density since the resistors do not have to occupy a large amount of space on the active surface of a semiconductor integrated circuit chip.
1. A semiconductor device, comprising:
a semiconductor substrate;
a buffer layer disposed on the semiconductor substrate, wherein the buffer layer comprises a first buffer layer and a second buffer layer, wherein the first buffer layer comprises a first layer of epitaxial compound semiconductor material that is epitaxially grown on the semiconductor substrate, wherein the second buffer layer comprises a second layer of epitaxial compound semiconductor material that is epitaxially grown on the first buffer layer, wherein the first and second layers of epitaxial compound semiconductor material are formed of different compositions of compound semiconductor material;
an active device layer disposed on the buffer layer, wherein the active device layer comprises a layer of epitaxial semiconductor material that is epitaxially grown on the buffer layer;
a contact plug disposed within a contact opening formed in the second buffer layer; and
a buried resistor disposed within a cavity formed within the first buffer layer below the second buffer layer and the active device layer, wherein a portion of the cavity within the first buffer layer comprises an undercut region which undercuts a portion of the second buffer layer surrounding the contact plug within the contact opening formed in the second buffer layer such that a portion of the buried resistor within the undercut region of the cavity is disposed underneath a bottom surface of the second buffer layer;
wherein the contact plug is connected to the buried resistor;
wherein the buffer layer serves to match a lattice constant of the semiconductor substrate to a lattice constant of the layer of epitaxial semiconductor material of the active device layer.
2. The device of claim 1 , wherein the contact plug and the buried resistor are formed of a same material.
3. The device of claim 1 , further comprising an ohmic contact formed on a surface of the contact plug exposed through the active device layer.
4. The device of claim 1 , further comprising a trench isolation structure formed within the active device layer and the buffer layer to define a resistor region for the buried resistor.
5. The device of claim 1 , wherein the layer of epitaxial semiconductor material of the active device layer comprises a third layer of epitaxial compound semiconductor material which is different in composition from the first and second layers of epitaxial compound semiconductor material.
6. The device of claim 5 , wherein the first, second, and third layers of epitaxial compound semiconductor material are formed of III-V compound semiconductor materials.
7. The device of claim 1 , further comprising an insulating liner disposed between the buried resistor and the buffer layer.
8. A semiconductor integrated circuit chip comprising the semiconductor device of claim 1 .
9. The device of claim 1 , wherein the buried resistor comprises polysilicon.
10. The device of claim 1 , wherein the semiconductor substrate comprises silicon.
11. The device of claim 1 , wherein the semiconductor substrate comprises III-V compound semiconductor material.
12. The device of claim 1 , wherein the buried resistor comprises a straight elongated profile.
13. The device of claim 1 , wherein the buried resistor comprises a meandering profile.
14. The device of claim 1 , wherein the active device layer is epitaxially grown on the second buffer layer.