Vertical transistors with buried metal silicide bottom contact
A method of fabricating the vertical field effect transistor includes forming a dielectric layer on a metal semiconductor alloy layer that is present on a substrate of a semiconductor material. The dielectric layer is bonded to a supporting substrate. The substrate of the semiconductor material is cleaved, wherein a remaining portion of the semiconductor material provides a semiconductor surface layer in direct contact with the metal semiconductor alloy layer. A vertical fin type field effect transistor (FinFET) is formed atop the stack of the semiconductor surface layer, the metal semiconductor alloy layer, the dielectric layer and the supporting substrate, wherein the semiconductor surface layer provides at least one of a source region or a drain region of the FinFET and the metal semiconductor alloy provides a contact to the source region or the drain region of the FinFET.
1. A semiconductor device comprising:
a material stack including a surface semiconductor layer present on a metal semiconductor alloy layer;
a first of a source region or a drain region present in the surface semiconductor layer, the surface semiconductor layer including the first of the source or the drain region having a first portion that extends continuously across an entirety of a width of the semiconductor device, and a second portion that has a pedestal geometry that does not extend the entirety of the width of the semiconductor device;
a vertically orientated channel having a first end contacting and aligned with the second portion of the surface semiconductor layer that has the pedestal geometry;
a gate structure in direct contact with the vertically orientated channel;
a second of the source region or the drain region present at a second end of the vertically oriented channel that is opposite said first end of the vertically orientated channel; and
a via contact in electrical communication with the metal semiconductor alloy layer providing a contact to said first of said source region or said drain region of the semiconductor device, wherein the metal semiconductor alloy layer extends continuously across the entirety of the width of the semiconductor device including being present directly underlying a portion of the surface semiconductor layer that is present directly underlying an entirety of the vertically , orientated channel.
2. The semiconductor device of claim 1 , wherein the semiconductor device is a vertically orientated n-type or p-type FinFET.
3. The semiconductor device of claim 1 , wherein the metal semiconductor alloy is a silicide selected from the group consisting of tungsten silicon, molybdenum silicide, tantalum silicide and combinations thereof.
4. The semiconductor device of claim 1 further comprising an interlevel dielectric of a silicon containing dielectric and said via contact extending through the interlevel dielectric into electrical communication with the metal semiconductor alloy.
5. The semiconductor device 1 , wherein an active region of the semiconductor device has a width defined by isolation regions positioned on opposing sides of the semiconductor device.
6. The semiconductor device 1 , wherein the material stack further comprises;
a dielectric layer, wherein the metal semiconductor alloy layer is present on the dielectric layer; and
a supporting substrate, wherein the dielectric layer is present on the supporting substrate.
7. The semiconductor device of claim 1 , wherein the semiconductor surface layer comprises a thickness ranging from 5 nm to 100 nm.