Vertical schottky contact FET
A semiconductor structure containing a vertical Schottky contact transistor is provided in which the contact resistance as well as the junction resistance is improved. The vertical Schottky contact transistor includes a bottom Schottky contact source/drain structure and a top Schottky contact source/drain structure located at opposing ends of a semiconductor channel region. The bottom Schottky contact source/drain structure includes a base portion and a vertically extending portion.
1. A semiconductor structure comprising:
a vertical field effect transistor located above a substrate, said vertical field effect transistor comprising:
a bottom Schottky contact source/drain structure located directly on a surface of said substrate, said bottom Schottky contact source/drain structure comprises a base portion and a vertically extending portion;
a semiconductor channel region extending vertically upwards from a surface of said base portion of said bottom Schottky contact source/drain structure;
a top Schottky contact source/drain structure located on a topmost surface of said semiconductor channel region; and
a gate structure located on each side of said semiconductor channel region, wherein said vertically extending portion of said bottom Schottky contact source/drain structure has a topmost surface that is coplanar with a topmost surface of said top Schottky contact source/drain structure.
2. The semiconductor structure of claim 1 , wherein said substrate comprises a bulk semiconductor substrate, a first semiconductor material layer of a first conductivity type located on a surface of said bulk semiconductor substrate, a second semiconductor material layer of a second conductivity type different from said first conductivity type located on a surface of said first semiconductor material layer.
3. The semiconductor of claim 2 , wherein a topmost surface of said second semiconductor material layer directly contacts a bottommost surface of said base portion of said bottom Schottky contact source/drain structure.
4. The semiconductor structure of claim 1 , wherein said substrate comprises a handle substrate and an insulator layer.
5. The semiconductor structure of claim 4 , wherein a topmost surface of said insulator layer directly contacts a bottommost surface of said base portion of said bottom Schottky contact source/drain structure.
6. The semiconductor structure of claim 1 , further comprising a bottom spacer separating each gate structure from said base portion of said bottom Schottky contact source/drain structure.
7. The semiconductor structure of claim 6 , further comprising a top spacer located on a topmost surface of each gate structure.
8. The semiconductor structure of claim 1 , further comprising a middle-of-the line (MOL) dielectric material surrounding said vertical field effect transistor, wherein said vertical extending portion of said bottom Schottky contact source/drain structure is located in an opening present in said (MOL) dielectric material.
9. The semiconductor structure of claim 8 , further comprising a gate contact structure contacting one of said gate structures and located in another opening present in said MOL dielectric material.
10. The semiconductor structure of claim 9 , wherein a topmost surface of said MOL dielectric material is coplanar with a topmost surface of said gate contact structure.
11. The semiconductor structure of claim 10 , wherein said topmost surfaces of said MOL dielectric material and said gate contact structure are coplanar with said topmost surface of said vertically extending portion of said bottom Schottky contact source/drain structure.
12. The semiconductor structure of claim 1 , wherein said top Schottky contact source/drain structure has sidewall surfaces that are vertically aligned to sidewall surfaces of said semiconductor channel region.
13. The semiconductor structure of claim 1 , wherein each of said gate structures comprises a gate dielectric material portion, a work function metal portion and a gate conductor portion.
14. The semiconductor structure of claim 1 , wherein each of said bottom Schottky contact source/drain structure and said top Schottky contact source/drain structure comprises a metal silicide.
15. The semiconductor structure of claim 1 , wherein each of said bottom Schottky contact source/drain structure and said top Schottky contact source/drain structure comprises a rare earth silicide.
16. A semiconductor structure comprising:
a vertical field effect transistor located above a substrate, said vertical field effect transistor comprising:
a bottom Schottky contact source/drain structure located directly on a surface of said substrate, said bottom Schottky contact source/drain structure comprises a base portion and a vertically extending portion;
a semiconductor channel region extending vertically upwards from a surface of said base portion of said bottom Schottky contact source/drain structure;
a top Schottky contact source/drain structure located on a topmost surface of said semiconductor channel region; and
a gate structure located on each side of said semiconductor channel region, wherein sidewall surfaces of said semiconductor channel region are vertically coincident with sidewall surfaces of said top Schottky contact source/drain structure.
17. The semiconductor structure of claim 16 , wherein each of said bottom Schottky contact source/drain structure and said top Schottky contact source/drain structure comprises a metal silicide.
18. The semiconductor structure of claim 16 , wherein each of said bottom Schottky contact source/drain structure and said top Schottky contact source/drain structure comprises a rare earth silicide.
19. The semiconductor structure of claim 16 , wherein said substrate comprises a bulk semiconductor substrate, a first semiconductor material layer of a first conductivity type located on a surface of said bulk semiconductor substrate, a second semiconductor material layer of a second conductivity type different from said first conductivity type located on a surface of said first semiconductor material layer, and wherein a topmost surface of said second semiconductor material layer directly contacts a bottommost surface of said base portion of said bottom Schottky contact source/drain structure.
20. The semiconductor structure of claim 16 , wherein said substrate comprises a handle substrate and an insulator layer, and wherein a topmost surface of said insulator layer directly contacts a bottommost surface of said base portion of said bottom Schottky contact source/drain structure.