Testing of semiconductor chips with microbumps

1. A device comprising:

a test pad on a chip;

a first microbump having a first surface area that is less than a surface area of the test pad;

a first conductive path coupling the test pad to the first microbump;

a second microbump having a second surface area that is less than the surface area of the test pad; and

a second conductive path coupling the test pad to the second microbump.

2. The device of claim 1 , wherein the test pad has an outer perimeter which is a polygon, and wherein the first conductive path couples the first microbump to a first side of the polygon and the second conductive path couples the second microbump to a second side of the polygon.

3. The device of claim 2 , wherein the first side of the polygon is bisected by a first line passing through a center of the polygon, and the second side of the polygon is bisected by a second line passing through the center of the polygon, the first line and the second line being separated by an angle ranging between ninety-degrees and two-hundred-and-seventy-degrees.

4. The device of claim 2 , wherein the first side of the polygon is bisected by a first line passing through a center of the polygon, and the second side of the polygon is bisected by a second line passing through the center of the polygon, the first line and the second line being separated by an angle of approximately ninety-degrees.

5. The device of claim 2 , wherein the first side of the polygon is bisected by a first line passing through a center of the polygon, and the second side of the polygon is bisected by a second line passing through the center of the polygon, the first line and the second line being separated by an angle of approximately forty-five-degrees.

6. The device of claim 2 , wherein the first conductive path consists of a linear segment that couples the first microbump directly to the first side of the polygon.

7. The device of claim 2 , wherein the first microbump and the second microbump are included on a current loop path, the current loop path having a first end coupled to a first side of the polygon and having a second end coupled to a second side of the polygon.

8. The device of claim 1 , wherein the first conductive path is fully independent of the second conductive path.

9. The device of claim 1 , wherein the first conductive path and the second conductive path share a trunk portion that is coupled to the test pad, the first conductive path branching from the trunk portion in a first direction to couple the trunk portion to the first microbump, and the second conductive path branching from the trunk portion in a second direction to couple the trunk portion to the second microbump.

10. The device of claim 1 , wherein the second conductive path includes the first microbump.

11. The device of claim 1 , wherein a minimum width of the test pad is at least 60 microns (μm).

12. The device of claim 1 , wherein a diameter or minimum width of the first microbump ranges from about 75 μm to about 150 μm.

13. The device of claim 1 , wherein a shape of the test pad is selected from the group consisting of a square, a rectangle, a circle, a hexagon, and an octagon.

14. A device comprising:

a chip comprising a test pad and a microbump pad which are disposed over a semiconductor substrate, wherein the test pad is electrically coupled to the microbump pad, wherein a width of the microbump pad is less than a width of the test pad;

a first passivation material disposed over the semiconductor substrate, the first passivation material having a first opening over the test pad and a second opening over the microbump pad; and

a second passivation material disposed over the first passivation material, the second passivation material filling the first opening and covering the test pad.

15. The device of claim 14 , further comprising:

a conductive structure arranged in the second opening and extending through the second passivation material, the conductive structure having a lower surface electrically coupled to the microbump pad and having an upper surface that is left uncovered by the second passivation material.

16. The device of claim 14 , wherein the test pad has surface damage from a probe.

17. The device of claim 14 , wherein a minimum width of the test pad is at least 60 microns (μm), and wherein a diameter or minimum width of the microbump pad is no larger than about 150 μm.

18. A package comprising:

a substrate having an upper surface and a lower surface with a through substrate via (TSV) extending between the upper surface and the lower surface, wherein a plurality of conductive bump structures are disposed on the lower surface of the substrate;

a semiconductor chip disposed over the substrate and comprising a plurality of microbump pad structures on a lower surface of the semiconductor chip;

wherein a microbump pad structure of the plurality of microbump pad structures has a surface area which is less than a surface area of a bump structure of the plurality of conductive bump structures, and wherein the microbump pad structure is electrically coupled to the bump structure through the TSV; and

wherein at least two microbump pad structures of the plurality of microbump pad structures are each electrically coupled to the bump structure.

19. The package of claim 18 , further comprising:

a first conductive path coupling a first microbump pad structure of the plurality of microbump pad structures to the bump structure; and

a second conductive path coupling a second microbump pad structure of the plurality of microbump pad structures to the bump structure;

wherein the first microbump pad structure and the second microbump pad structure each have a surface area which is less than a surface area of the bump structure.

20. The package of claim 18 , further comprising:

a test pad disposed on the lower surface of the chip and being spaced apart from the microbump pad structures, the test pad having a width that is greater than that of a microbump pad structure.