Arithmetic processing device and method of controlling arithmetic processing device
An arithmetic processing device includes: a first register configured to hold data to be used to execute an instruction; a second register configured to hold a portion of the data held in the first register; a computing circuit configured to execute computation using the data held in the second register; a first error detector configured to detect whether or not an error is included in the data to be transferred by the first register to the second register; a controller configured to interrupt the execution of the instruction if the first error detector detects the error in the data; and an error corrector configured to correct the error in the data held in the first register if the first error detector detects the error in the data.
1. An arithmetic processing device comprising:
a first register configured to hold first data to be used to execute an instruction;
a second register coupled to the first register and configured to hold, as second data, a portion of the first data held in the first register which is to be transferred by the first register to the second register;
a computing circuit coupled to the second register and configured to execute computation using the second data, held in the second register and transferred by the second register to the computing circuit, according to the instruction;
a first error detector coupled to the first register and configured to detect whether or not an error is included in the portion of the first data to be transferred by the first register to the second register and before the portion of the first data is transferred from the second register to the computing circuit;
a second error detector coupled to the second register and configured to detect an error in the second data to be transferred by the second register to the computing circuit;
a replacing circuit configured to replace the second data having the error with dummy data that is determined not to have an error by the second error detector before the transfer of the portion of the first data having an error detected by the first error detector to the computing circuit if the first error detector detects the error in the portion of the first data;
a controller, coupled to the first error detector and to the computing circuit, and configured to interrupt the execution of the instruction if the first error detector detects the error in the portion of the first data; and
an error corrector coupled to the controller and configured to correct the error in the first data held in the first register if the first error detector detects the error in the portion of the first data.
2. The arithmetic processing device according to claim 1 ,
wherein the replacing circuit replaces the portion of the first data having an error output from the first register section with the dummy data and transfers the dummy data to the second register.
3. The arithmetic processing device according to claim 1 ,
wherein the replacing circuit replaces the second data having the error output from the second register section with the dummy data and transfers the dummy data to the computing circuit.
4. The arithmetic processing device according to claim 1 ,
wherein if the first error detector detects the error in the portion of the first data, the controller interrupts the execution of the instruction by stopping the computation by the computing circuit.
5. The arithmetic processing device according to claim 4 ,
wherein after the first error corrector corrects the error in the first data held in the first register, the controller re-executes the interrupted instruction.
6. The arithmetic processing device according to claim 1 ,
wherein if the first error detector detects the error in the portion of the first data, the controller stops a commit for writing a result of the computation by the computing circuit to the second register and interrupts the execution of the instruction.
7. A method of controlling an arithmetic processing device including a first register configured to hold first data to be used to execute an instruction, a second register configured to hold, as second data, a portion of the first data held in the first register which is to be transferred from the first register to the second register, and a computing circuit configured to execute computation using the second data held in the second register, comprising:
causing a first error detector included in the arithmetic processing device to detect whether or not an error is included in the portion of the first data to be transferred by the first register to the second register and before the portion of the first data is transferred from the second register to the computing circuit;
causing a second error detector included in the arithmetic processing device to detect an error in the second data to be transferred by the second register to the computing circuit;
causing a replacing circuit included in the arithmetic processing device to replace the second data having the error with dummy data that is determined not to have an error by the second error detector before the transfer of the portion of the first data having an error detected by the first error detector to the computing circuit if the first error detector detects the error in the portion of the first data;
causing a controller included in the arithmetic processing device to interrupt the execution of the instruction if the first error detector detects the error in the portion of the first data; and
causing an error corrector included in the arithmetic processing device to correct the error in the first data held in the first register if the first error detector detects the error in the portion of the first data.