Equivalence checking of analog models

1. A computer-implemented method for design analysis comprising:

extracting an input signal set using a first representation of a semiconductor circuit;

creating a common input stimulus signal set for a second representation of the semiconductor circuit based on the input signal set extracted from the first representation of the semiconductor circuit;

replaying the common input stimulus signal set against the second representation of the semiconductor circuit;

generating first output waveforms for outputs of the first representation and second output waveforms for outputs of the second representation of the semiconductor circuit using the common input stimulus signal set;

preparing first sampling times for the first output waveforms;

preparing second sampling times for the second output waveforms;

generating a vector of comparison objects, wherein the vector of comparison objects includes objects in both the first output waveforms and the second output waveforms; and

determining a deviation between a first object in the first output waveforms and a second object in the second output waveforms wherein the deviation exceeds a tolerance value.

2. The method of claim 1 wherein the extracting the input signal set from the first representation of the semiconductor circuit is based on simulating the first representation and providing results of the simulating the first representation to a first signal dump file.

3. The method of claim 2 wherein the generating the first output waveforms is based on the simulating the first representation wherein the first output waveforms are provided to the first signal dump file.

4. The method of claim 2 wherein the replaying the common input stimulus signal set against the second representation includes simulating the second representation wherein the second output waveforms are provided to a second signal dump file.

5. The method of claim 4 wherein the simulating of the first representation is accomplished in context of a mixed-language co-simulation comprising a SPICE™ simulator and a Verilog™ simulator.

6. The method of claim 4 wherein the performing equivalence checking between the first output waveforms and the second output waveforms includes comparing the first signal dump file and the second signal dump file.

7. The method of claim 1 wherein the first representation of the semiconductor circuit includes transistor level modeling.

8. The method of claim 1 wherein the first representation of the semiconductor circuit includes analog modeling.

9. The method of claim 1 wherein the second representation of the semiconductor circuit includes behavioral modeling.

10. The method of claim 1 wherein the second representation of the semiconductor circuit includes structural modeling.

11. The method of claim 1 wherein the creating the common input stimulus signal set for the second representation includes time shifting the input signal set extracted using the first representation of the semiconductor circuit.

12. The method of claim 1 wherein the creating the common input stimulus signal set for the second representation includes voltage shifting the input signal set extracted from the first representation of the semiconductor circuit.

13. The method of claim 1 further comprising time shifting the first output waveforms or the second output waveforms as part of the performing equivalence checking.

14. The method of claim 1 further comprising voltage shifting the first output waveforms or the second output waveforms as part of the performing equivalence checking.

15. The method of claim 1 wherein the performing equivalence checking includes evaluating using a tolerance value.

16. The method of claim 15 wherein the tolerance value includes a time tolerance.

17. The method of claim 15 wherein the tolerance value includes a voltage tolerance.

18. The method of claim 15 wherein the tolerance value includes a current tolerance.

19. The method of claim 15 wherein the tolerance value includes a frequency tolerance.

20. The method of claim 1 further comprising updating the first representation of the semiconductor circuit based on the equivalence checking.

21. The method of claim 1 further comprising updating the second representation of the semiconductor circuit based on the equivalence checking.

22. The method of claim 1 further comprising mapping signals from the first output waveforms to signals from the second output waveforms.

23. A computer system for design analysis comprising:

a memory which stores instructions;

one or more processors coupled to the memory wherein the one or more processors are configured to:

extract an input signal set using a first representation of a semiconductor circuit;

create a common input stimulus signal set for a second representation of the semiconductor circuit based on the input signal set extracted from the first representation of the semiconductor circuit;

replay the common input stimulus signal set against the second representation of the semiconductor circuit;

generate first output waveforms for outputs of the first representation and second output waveforms for outputs of the second representation of the semiconductor circuit using the common input stimulus signal set;

prepare first sampling times for the first output waveforms;

prepare second sampling times for the second output waveforms;

generate a vector of comparison objects, wherein the vector of comparison objects includes objects in both the first output waveforms and the second output waveforms; and

determine a deviation between a first object in the first output waveforms and a second object in the second output waveforms wherein the deviation exceeds a tolerance value.