DRAM cell for reducing layout area and fabricating method thereof

1. A fabricating method of a dynamic random access memory (DRAM) cell formed to correspond to an intersecting point between a word line and a bit line and including a storage and a cell transistor, wherein the storage is configured to store charges and the cell transistor is configured to form a transmission channel for electrically connecting the bit line to the storage according to a voltage applied to a gate electrode that is formed as a part of the word line, where the transmission channel includes a first side and a second side, the fabricating method comprising:

forming a facing bar that has a constant width and a constant height with respect to a horizontal surface of a semiconductor substrate and extends in a direction of the word line, where the facing bar includes a first side surface and a second side surface;

forming a gate of the cell transistor on the first side surface of the facing bar, wherein the transmission channel of the cell transistor is formed to be in contact with the first side surface of the facing bar and the horizontal surface of the semiconductor substrate;

forming a bit line plug that is electrically connected to the first side of the transmission channel, which is formed on the first side surface of the facing bar, wherein the bit line plug is electrically connected to the bit line; and

forming the storage that is electrically connected to the second side of the transmission channel, which is formed on the horizontal surface of the semiconductor substrate,

wherein a gate electrode of another DRAM cell paired with the DRAM cell is formed at the second side surface of the facing bar, and

the bit line plug is electrically connected to one side of a transmission channel of the another DRAM cell paired with the DRAM cell, and

wherein the forming of the facing bar includes:

forming a substrate insulating film on the semiconductor substrate;

forming a separation region to form an active separation region on the semiconductor substrate, on which the substrate insulating film is formed, so as to secure an active region of the DRAM cell;

etching the semiconductor substrate at which the active separation region is formed; and

forming the facing bar.

2. The fabricating method of claim 1 , wherein the forming of the gate of the cell transistor includes: implanting channel impurities into the first side surface of the facing bar and the horizontal surface of the semiconductor substrate to form the transmission channel of the cell transistor, and then forming a channel oxide film; and forming a gate electrode of the cell transistor to be in contact with the first side surface of the facing bar and the horizontal surface of the semiconductor substrate, wherein the channel oxide film is formed on the first side surface of the facing bar and the horizontal surface.

3. The fabricating method of claim 1 , wherein the forming of the bit line plug includes:

forming a bit line contact hole above the facing bar; and

filling the bit line contact hole with a first conductive material and forming the bit line plug, wherein the bit line plug is electrically connected to the one side of the transmission channel of the cell transistor.

4. The fabricating method of claim 1 , wherein the forming of the storage includes:

forming a storage contact hole by exposing the horizontal surface of the semiconductor substrate, and then forming a storage plug by filling the storage contact hole with a second conductive material, wherein the storage plug is electrically connected to the other side of the transmission channel; and

forming the storage that is electrically connected to the storage plug.