Method for making three dimensional complementary metal oxide semiconductor carbon nanotube thin film transistor circuit
A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.
1. A method for making metal oxide semiconductor carbon nanotube thin film transistor circuit, the method comprises:
forming a first semiconductor carbon nanotube layer on an insulating substrate;
applying a first drain electrode and a first source electrode to be electrically connected to the first semiconductor carbon nanotube layer;
depositing a functional dielectric layer on a surface of the first semiconductor carbon nanotube layer;
applying a common gate electrode on the functional dielectric layer, wherein the common gate electrode is insulated from the first semiconductor carbon nanotube layer;
depositing an insulating layer to cover the first semiconductor carbon nanotube layer, the first drain electrode, the first source electrode and the common gate electrode;
forming a second semiconductor carbon nanotube layer on the insulating layer, wherein the second semiconductor carbon nanotube layer is insulated from the common gate electrode;
exposing part of the first drain electrode by making a through hole at least on the insulating layer; and
applying a second drain electrode and a second source electrode to be electrically connected to the second semiconductor carbon nanotube layer, wherein the second drain electrode extends into the through hole and is in electrically connected to the first drain electrode; wherein the first semiconductor carbon nanotube layer, the first drain electrode, the first source electrode, the functional dielectric layer, and the common gate electrode form a first thin film transistor; the common gate electrode, the insulating layer, the second semiconductor carbon nanotube layer, the second drain electrode, and the second source electrode form a second thin film transistor; and the first thin film transistor and the second thin film transistor share the common gate electrode; wherein the method for making the metal oxide semiconductor carbon nanotube thin film transistor circuit leaves a portion of the second semiconductor carbon nanotube layer between the second drain electrode and the second source electrode uncovered, whereby the portion of the second semiconductor carbon nanotube layer between the second drain electrode and the second source electrode is exposed and uncovered.
2. The method of claim 1 , wherein the insulating substrate is a polymer film.
3. The method of claim 1 , wherein each of the first semiconductor carbon nanotube layer and the second semiconductor carbon nanotube layer comprises a plurality of single-walled carbon nanotubes connected with each other to form a conductive network.
4. The method of claim 1 , wherein the functional dielectric layer comprises material selected from the group consisting of hafnium oxide, yttrium oxide, silicon nitride, magnesium oxide, potassium, and organic polymers.
5. The method of claim 1 , wherein the functional dielectric layer comprises a magnesium oxide layer and an aluminum oxide layer.
6. The method of claim 1 , wherein the functional dielectric layer comprises a silicon nitride layer and the insulating layer comprises an aluminum oxide layer.
7. The method of claim 1 , wherein the insulating layer comprises a polymer film.
8. The method of claim 1 , wherein the making the through hole comprises etching the insulating layer and the functional dielectric layer.
9. The method of claim 1 , wherein the first thin film transistor is top gate type and the second thin film transistor is bottom back type.
10. The method of claim 1 , wherein the first semiconductor carbon nanotube layer is n-type and the second semiconductor carbon nanotube layer is p-type.
11. The method of claim 1 , wherein the common gate electrode is sandwiched between the first semiconductor carbon nanotube layer and the second semiconductor carbon nanotube layer.