Display device and gate driving circuit thereof
A display device and a gate driver circuit of the display device are disclosed. The display device includes a shift register that shifts a gate pulse in accordance with a shift clock and sequentially supplies the gate pulse to gate lines. At least one stage of the shift register includes a discharge blocking node connected to a source terminal of the second transistor, and a discharge blocking circuit configured to charge the discharge blocking node when the Q node is charged, and discharge the discharge blocking node when the Q node is discharged.
1. A display device comprising:
a display panel including:
a plurality of pixels, that are connected to data lines and gate lines, the plurality of pixels divided in a plurality of blocks that are time division driven in a plurality of display periods within one frame period, and
a plurality of touch sensors connected to the pixels;
a touch sensing circuit configured to drive the plurality of touch sensors with a touch sensor driving signal during a touch sensing period between two of the display periods, and sense a touch input during the touch sensing period;
a display driving circuit configured to write data of an input image to the pixels in the plurality of display periods, the display driving circuit comprising a shift register that shifts a gate pulse in accordance with a shift clock and sequentially supplies the gate pulse to the gate lines, the shift register having a plurality of stages, each stage of the shift register including:
a Q node controlling a pull-up transistor increasing a voltage of the gate pulse,
a first transistor charging the Q node in response to a start signal or an output signal of a previous stage, and
a pair of transistors switching on and off a discharge path of the Q node in response to an output signal of a next stage, and
at least one of the stages including:
a discharge blocking circuit coupled to source terminals of the pair of transistors, and configured to charge the source terminal of the pair of transistors when the Q node is charged, and discharge the source terminals of the pair of transistors when the Q node is discharged.
2. The display device of claim 1 , wherein each stage further includes a QB node controlling a pull-down transistor decreasing the voltage of the gate pulse.
3. The display device of claim 2 , wherein the pair of transistors includes:
a second transistor configured to discharge the Q node in response to the output signal of the next stage; and
a third transistor configured to discharge the Q node in response to a voltage of the QB node.
4. The display device of claim 3 , wherein the discharge blocking circuit includes:
a first discharge control switch charging the source terminals of the pair of transistors in response to the start signal or the output signal of the previous stage;
a second discharge control switch discharging the source terminals of the pair of transistors in response to the output signal of the next stage; and
a third discharge control switch discharge the source terminals of the pair of transistors in response to the voltage of the QB node.
5. The display device of claim 3 , wherein the discharge blocking circuit includes:
a first discharge control switch charging the source terminals of the pair of transistors in response to the start signal or the output signal of the previous stage;
a second discharge control switch discharging the source terminals of the pair of transistors in response to the output signal of the next stage; and
a diode connected to the source terminals of the pair of transistors.
6. The display device of claim 3 , wherein the discharge blocking circuit includes:
a first discharge control switch charging the source terminals of the pair of transistors in response to the start signal or the output signal of the previous stage;
a second discharge control switch discharging the source terminals of the pair of transistors in response to the output signal of the next stage; and
a capacitor connected to the source terminals of the pair of transistors.
7. The display device of claim 3 , wherein the discharge blocking circuit includes:
a first discharge control switch charging the source terminals of the pair of transistors in response to the start signal or the output signal of the previous stage;
a second discharge control switch discharging the source terminals of the pair of transistors in response to the output signal of the next stage;
a resistor connected to the source terminals of the pair of transistors; and
a capacitor connected to the source terminals of the pair of transistors.
8. The display device of claim 1 , wherein the discharge blocking circuit includes:
a first discharge control switch charging the source terminals of the pair of transistors in response to the start signal or the output signal of the previous stage;
a diode connected to the source terminals of the pair of transistors; and
a capacitor connected to the source terminals of the pair of transistors.
9. The display device of claim 1 , wherein the discharge blocking circuit includes:
a first discharge control switch charging the source terminals of the pair of transistors in response to the start signal or the output signal of the previous stage;
a resistor connected to the source terminals of the pair of transistors; and
a capacitor connected to the source terminals of the pair of transistors.
10. The display device of claim 1 , wherein only a first stage corresponding to a first gate line of each block includes the discharge blocking circuit.
11. The display device of claim 1 , wherein every stage of the shift register includes the discharge blocking circuit.
12. A gate driver circuit of a display device including a display panel including pixels that are connected to data lines and gate lines and are division-driven based on a plurality of blocks, and a plurality of touch sensors connected to the pixels, the gate driver circuit comprising:
a shift register configured to shift a gate pulse in accordance with a shift clock and sequentially supply the gate pulse to the gate lines, the shift register having a plurality of stages;
wherein each stage of the shift register includes:
a Q node controlling a pull-up transistor increasing a voltage of the gate pulse,
a first transistor charging the Q node in response to a start signal or an output signal of a previous stage, and
a pair of transistors switching on and off a discharge path of the Q node in response to an output signal of a next stage; and
wherein at least one of the stages includes:
a discharge blocking circuit coupled to source terminals of the pair of transistors, and configured to charge the source terminals of the pair of transistors when the Q node is charged, and discharge the source terminals of the pair of transistors when the Q node is discharged.
13. The gate driver circuit of claim 12 , wherein each stage further includes a QB node controlling a pull-down transistor decreasing the voltage of the gate pulse.
14. The gate driver circuit of claim 13 , wherein the pair of transistors includes:
a second transistor configured to discharge the Q node in response to the output signal of the next stage; and
a third transistor configured to discharge the Q node in response to a voltage of the QB node.
15. The gate driver circuit of claim 14 , wherein the discharge blocking circuit includes:
a first discharge control switch charging the source terminals of the pair of transistors in response to the start signal or the output signal of the previous stage;
a second discharge control switch discharging the source terminals of the pair of transistors in response to the output signal of the next stage; and
a third discharge control switch discharge the source terminals of the pair of transistors in response to the voltage of the QB node.
16. The gate driver circuit of claim 14 , wherein the discharge blocking circuit includes:
a first discharge control switch charging the source terminals of the pair of transistors in response to the start signal or the output signal of the previous stage;
a second discharge control switch discharging the source terminals of the pair of transistors in response to the output signal of the next stage; and
a diode connected to the source terminals of the pair of transistors.
17. The gate driver circuit of claim 14 , wherein the discharge blocking circuit includes:
a first discharge control switch charging the source terminals of the pair of transistors in response to the start signal or the output signal of the previous stage;
a second discharge control switch discharging the source terminals of the pair of transistors in response to the output signal of the next stage; and
a capacitor connected to the source terminals of the pair of transistors.
18. The gate driver circuit of claim 14 , wherein the discharge blocking circuit includes:
a first discharge control switch charging the source terminals of the pair of transistors in response to the start signal or the output signal of the previous stage;
a second discharge control switch discharging the source terminals of the pair of transistors in response to the output signal of the next stage;
a resistor connected to the source terminals of the pair of transistors; and
a capacitor connected to the source terminals of the pair of transistors.
19. The gate driver circuit of claim 12 , wherein the discharge blocking circuit includes:
a first discharge control switch charging the source terminals of the pair of transistors in response to the start signal or the output signal of the previous stage;
a diode connected to the source terminals of the pair of transistors; and
a capacitor connected to the source terminals of the pair of transistors.
20. The gate driver circuit of claim 12 , wherein the discharge blocking circuit includes:
a first discharge control switch charging the source terminals of the pair of transistors in response to the start signal or the output signal of the previous stage;
a resistor connected to the source terminals of the pair of transistors; and
a capacitor connected to the source terminals of the pair of transistors.