Semiconductor integrated circuit device having a standard cell which includes a fin
Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.
1. A semiconductor integrated circuit device comprising:
a standard cell having a first fin and a second fin each of which extends in a first direction in a first conductivity-type region and a third fin and a fourth fin extending in the first direction in a second conductivity-type region which is different from the first conductivity-type region, wherein
the standard cell comprises:
a first active transistor including the first fin, the second fin, and a first gate line extending in a second direction perpendicular to the first direction, nodes of the first fin and the second fin at both sides of the first gate line in the first direction being source and drain of the first active transistor;
a first dummy transistor including the first fin, the second fin, and a first dummy gate line extending in the second direction, nodes of the first fin and the second fin at both sides of the first dummy gate line in the first direction being source and drain of the first dummy transistor; and
a second active transistor including the third fin, the fourth fin, and a second gate line extending in the second direction at the same position as the first gate line in the first direction, nodes of the third fin and the fourth fin at both sides of the second gate line in the first direction being source and drain of the second active transistor, and
the first active transistor shares one of its source or drain with the first dummy transistor.
2. The semiconductor integrated circuit device of claim 1 , wherein the standard cell comprises:
a third transistor including the first fin, the second fin, and a third gate line extending in the second direction and provided on the opposite side of the first gate line from the first dummy gate line, nodes of the first fin and the second fin at both sides of the third gate line in the first direction being source and drain of the third transistor, and
the first active transistor shares another of its drain or source with the third transistor.
3. The semiconductor integrated circuit device of claim 2 , wherein the third transistor functions as a third active transistor.
4. The semiconductor integrated circuit device of claim 1 , wherein the node of the first active transistor shared with the first dummy transistor is its source to which a power supply potential is supplied.
5. The semiconductor integrated circuit device of claim 4 , wherein the source and drain, and the first dummy gate line of the first dummy transistor are all connected to a power supply line.
6. The semiconductor integrated circuit device of claim 1 , wherein the node of the first active transistor shared with the first dummy transistor is its drain, and the first dummy gate line of the first dummy transistor is connected to a power supply line.
7. The semiconductor integrated circuit device of claim 1 , wherein the standard cell comprises:
a third active transistor including the first fin, the second fin, and a third gate line extending in the second direction, nodes of the first fin and the second fin at both sides of the third gate line in the first direction being source and drain of the third active transistor, and
each of the first active transistor and the third active transistor shares both of its source and drain with associated ones of other transistors.
8. The semiconductor integrated circuit device of claim 7 , wherein the third active transistor shares one of its source or drain with a second dummy transistor.
9. The semiconductor integrated circuit device of claim 1 , wherein the standard cell comprises:
a fourth transistor including the third fin, the fourth fin, and a fourth gate line extending in the second direction at the same position as the first dummy gate line in the first direction, nodes of the third fin and the fourth fin at both sides of the fourth gate line in the first direction being source and drain of the fourth transistor, and
the second active transistor shares one of its source or drain with the fourth transistor.
10. The semiconductor integrated circuit device of claim 9 , wherein the fourth transistor functions as a fourth active transistor.
11. The semiconductor integrated circuit device of claim 9 , wherein the fourth transistor functions as a third dummy transistor.