Targeted recovery process

1. An apparatus comprising:

at least three processing circuits to perform redundant processing of common program instructions; and

error detection circuitry coupled to a plurality of signal nodes of each of said at least three processing circuits, said error detection circuitry comprising comparison circuitry to detect a mismatch between signals on corresponding signal nodes in said at least three processing circuits;

said plurality of signal nodes forming a first group of signal nodes and a second group of signal nodes; wherein

in response to said mismatch being detected in relation to corresponding signal nodes within said first group said error detection circuitry is configured to generate a first trigger for a full recovery process for resolving an error detected for an erroneous processing circuit using state information derived from at least two other processing circuits, and in response to said mismatch being detected in relation to corresponding signal nodes within said second group to generate a second trigger for a targeted recovery process for a subset of components of said erroneous processing circuit.

2. The apparatus according to claim 1 , wherein said targeted recovery process uses state information derived from said at least two other processing circuits.

3. The apparatus according to claim 1 , wherein said first group of signal nodes are external nodes of said at least three processing circuits.

4. The apparatus according to claim 1 , wherein said second group of signal nodes are internal nodes of said at least three processing circuits.

5. The apparatus according to claim 1 , wherein said subset of components are one or more storage structures.

6. The apparatus according to claim 5 , wherein said second group of signal nodes are signal paths connected to said one or more storage structures in each of said at least three processing circuits.

7. The apparatus according to claim 6 , wherein said signal paths connected to said storage structures are write interface signal paths.

8. The apparatus according to claim 1 , wherein performance of the targeted recovery process requires less processing resources than performance of the full recovery process.

9. The apparatus according to claim 1 , wherein said mismatch being detected in relation to corresponding signal nodes within said second group is indicative of erroneous data accessible to a processing pipeline of said erroneous processing circuit, and the corresponding signal nodes are located such that at a time when said mismatch is detected, said erroneous data has yet to be accessed by the processing pipeline of said erroneous processing circuit.

10. The apparatus according to claim 1 , wherein said mismatch being detected in relation to corresponding signal nodes within said first group is indicative of a need to restore a processing pipeline of said erroneous processing circuit.

11. The apparatus according to claim 1 , wherein said full recovery is performed for at least one component of a processing pipeline, and said subset of components comprises components other than those of said processing pipeline.

12. The apparatus according to claim 1 , further comprising recovery control circuitry to control said at least three processing circuits to perform said full recovery process in response to said first trigger and to control said at least three processing circuits to perform said targeted recovery process in response to said second trigger.

13. The apparatus according to claim 12 , wherein in response to said second trigger said recovery control circuitry is arranged to cause each of said at least three processing circuits to execute an interrupt service routine in order to perform said targeted recovery process.

14. The apparatus according to claim 12 , wherein in response to said second trigger said recovery control circuitry is arranged to cause each of said at least three processing circuits to perform a memory barrier operation to write contents stored within at least one storage structure to memory.

15. The apparatus according to claim 1 , wherein during performance of said targeted recovery process, said error detection circuitry is further configured to ignore a mismatch between a signal node on said erroneous processing circuit and corresponding signal nodes on the other processing circuits.

16. The apparatus according to claim 15 , wherein during performance of said targeted recovery process, said error detection circuitry is further configured to generate an unresolvable error signal when a mismatch is detected between signals on corresponding signal nodes of processing circuits other than said erroneous processing circuit.

17. The apparatus according to claim 7 , wherein said one or more storage structures comprises a register file, and said targeted recovery process comprises:

interrupting processing of the common program instructions by said at least three processing circuits;

causing each of the at least three processing circuits to drain contents of their register file to memory via majority voting circuitry to remove erroneous data;

restoring content in the register file of each of said at least three processing circuits from the memory; and

resuming processing of the common program instructions.

18. The apparatus according to claim 7 , wherein said one or more storage structures comprises a store buffer, and said targeted recovery process comprises:

interrupting processing of the common program instructions by said at least three processing circuits;

performing a memory barrier operation to cause each of the at least three processing circuits to store the data from their store buffer to memory via majority voting circuitry to remove erroneous data; and

resuming processing of the common program instructions.

19. An apparatus comprising:

at least three means for processing for performing redundant processing of common program instructions; and

means for detecting errors coupled to a plurality of signal nodes of each of said at least three processing means, said means for detecting errors comprising comparing means for detecting a mismatch between signals on corresponding signal nodes in said at least three means for processing;

said plurality of signal nodes forming a first group of signal nodes and a second group of signal nodes; wherein

in response to said mismatch being detected in relation to corresponding signal nodes within said first group said means for detecting errors is configured to generate a first trigger for a full recovery process for resolving an error detected for an erroneous means for processing using state information derived from at least two other means for processing, and in response to said mismatch being detected in relation to corresponding signal nodes within said second group to generate a second trigger for a targeted recovery process for a subset of components of said erroneous means for processing.

20. A method comprising:

performing redundant processing of common program instructions using at least three processing circuits;

detecting a mismatch between signals on corresponding signal nodes in said at least three processing circuits;

said signal nodes forming a first group of signal nodes and a second group of signal nodes; and

in response to detecting said mismatch in relation to corresponding signal nodes within said first group, generating a first trigger for a full recovery process for resolving an error detected for an erroneous processing circuit using state information derived from at least two other processing circuits, and in response to said mismatch being detected in relation to corresponding signal nodes within said second group, generating a second trigger for a targeted recovery process for a subset of components of said erroneous processing circuit.