Organic light-emitting diode display with pulse-width-modulated brightness control
A display may have an array of pixels arranged in rows and columns. Display driver circuitry may load data into the pixels via data lines that extend along the columns. The display driver circuitry may include gate driver circuitry that supplies horizontal control signals to rows of the pixels. The horizontal control signals may include emission enable signals for controlling emission enable transistors and scan signals for controlling switching transistors. During an emission phase of operation for the display, the emission enable signal may be pulse-width modulated by the emission control gate driver circuits in the gate driver circuitry to control the output of the light-emitting diodes. The emission control gate driver circuits may be controlled using an emission start signal and a pair of two-phase clocks.
1. A display, comprising:
a pixel array having rows and columns of pixels each having a light-emitting diode and a transistor coupled in series with the light-emitting diode; and
display driver circuitry that supplies data to the pixels via data lines and that supplies control signals to the pixels via gate lines, wherein the display driver circuitry includes a plurality of emission control gate driver circuits each of which produces a corresponding pulse-width-modulated emission enable signal that is supplied to the transistors of the pixels in one of the rows, wherein each emission control gate driver circuit receives first and second two-phase clocks and uses the first and second two-phase clocks to generate the corresponding pulse-width modulated emission enable signal, wherein the first two-phase clock has first and second clock signals with a first frequency, wherein the second two-phase clock has third and fourth clock signals with a second frequency that is different than the first frequency, and wherein the second clock signal is delayed with respect to the first clock signal while the fourth clock signal is delayed with respect to the third clock signal.
2. The display defined in claim 1 wherein the emission control gate driver circuits each receive a respective emission start signal.
3. The display defined in claim 2 wherein the pulse-width-modulated emission enable signal for each row serves as the emission start signal of a successive row and is received by the emission control gate driver circuit of the successive row.
4. The display defined in claim 3 wherein the pulse-width-modulated emission enable signal of each row is asserted during pulse-width-modulation on periods in which the light-emitting diodes of that row are turned on by turning on the transistors in that row using the pulse-width-modulated emission enable signal and is deasserted during pulse-wide-modulation off periods in which the light-emitting diodes of that row are turned off by turning off the transistors in that row using the pulse-width-modulated emission enable signal.
5. The display defined in claim 4 wherein the emission start signal is adjusted to control the pulse-width-modulation on periods and off periods.
6. The display defined in claim 5 wherein the pulse-width-modulation on periods and off periods have starting and ending times and wherein the first two-phase clock is a pulse width-modulation control clock and has two signals with edges that determine the starting and ending times in conjunction with the emission start signal.
7. The display defined in claim 6 wherein each pixel includes a drive transistor coupled in series with the transistor and the light-emitting diode.
8. The display defined in claim 7 wherein the third and fourth clock signals have edges that determine when the emission enable signal transitions during threshold voltage compensation operations.
9. The display defined in claim 1 wherein the first and second two-phase clocks control emission enable signal transitions.
10. The display defined in claim 9 wherein the first two-phase clock is a pulse-width-modulation control clock that controls transitions between pulse-width-modulation on periods in which the light-emitting diodes emit light and pulse-width-modulation off periods in which the light-emitting diodes do not emit light.
11. The display defined in claim 10 wherein the second two-phase clock is an emission control clock that controls emission enable signal transitions during threshold voltage compensation operations.
12. The display defined in claim 11 wherein each pixel includes a drive transistor coupled between the transistor and the light-emitting diode and wherein the threshold voltage compensation operations compensate for threshold voltage variations in the drive transistors.
13. A display, comprising:
an array of pixels each of which has a light-emitting diode, a drive transistor coupled to the light-emitting diode, an emission enable transistor coupled in series with the light-emitting diode and the drive transistor, and switching transistors; and
display driver circuitry that supplies data to the pixels via data lines and that supplies control signals to the pixels via gate lines, wherein the display driver circuitry includes emission control gate driver circuits each of which produces a corresponding pulse-width-modulated emission enable signal that is supplied to the emission enable transistors in a respective row of pixels in the array, wherein the emission control gate driver circuits each receive a pulse-width-modulation control clock, and wherein the pulse-width-modulation control clock controls transitions between pulse-width-modulation on periods in which the pulse-width-modulated emission enable signal is asserted and the light-emitting diodes emit light and pulse-width-modulation off periods in which the pulse-width-modulated emission enable signal is deasserted and the light-emitting diodes do not emit light.
14. The display defined in claim 13 wherein the emission control gate driver circuits each receive an emission control clock.
15. The display defined in claim 14 wherein the emission control clock controls emission enable signal transitions during threshold voltage compensation operations for the drive transistors.
16. Display driver circuitry for supplying control signals to organic light-emitting diode display pixels each of which has an organic light-emitting diode, a drive transistor coupled to the organic light-emitting diode, and an emission enable transistor coupled in series with the organic light-emitting diode and the drive transistor, comprising:
an emission control gate driver circuit that receives an emission start signal, that receives a two-phase emission control clock, that receives a two-phase pulse-width-modulation control clock, and that provides a pulse-width-modulated emission enable signal to the emission enable transistors to control light emission from the organic light-emitting diodes based at least on the emission start signal, the two-phase emission control clock, and the two-phase pulse-width-modulation control clock, wherein the two-phase emission control clock controls the pulse-width-modulated emission enable signal during a threshold voltage compensation period, and wherein the emission start signal and the two-phase pulse-width-modulation control clock control the pulse-width-modulated emission enable signal during an emission period.