Semiconductor device or electronic component including the same
View Patent ↗A semiconductor device includes a memory cell, a buffer circuit, a switch, first to p-th switch circuits, and first to p-th capacitors (p is an integer of 2 or more). The first to p-th switch circuits each include first to third terminals. The memory cell is electrically connected to a first electrode of the first capacitor and an input terminal of the buffer circuit through the switch. A second electrode of an i-th capacitor is electrically connected to a first terminal of an i-th switch circuit and a first electrode of an (i+1)th capacitor (i is an integer of 1 to (p−1)). A second electrode of the p-th capacitor is electrically connected to a first terminal of the p-th switch circuit. An output terminal of the buffer circuit is electrically connected to a second terminal of each of the first to p-th switch circuits. A third terminal of each of the first to p-th switch circuits is electrically connected to a wiring supplying a low-level potential.
1. A semiconductor device comprising:
a memory cell;
a circuit; and
a first wiring,
wherein the circuit comprises a buffer circuit, a first switch, first to p-th switch circuits, and first to p-th capacitors (p is an integer of 2 or more),
wherein the first to p-th switch circuits each comprise a first terminal, a second terminal, a third terminal, a second switch, and a third switch,
wherein in each of the first to p-th switch circuits, the first terminal is electrically connected to the second terminal through the second switch,
wherein in each of the first to p-th switch circuits, the first terminal is electrically connected to the third terminal through the third switch,
wherein a first electrode of the first capacitor is electrically connected to the memory cell,
wherein an input terminal of the buffer circuit is electrically connected to the memory cell through the first switch,
wherein a second electrode of an i-th capacitor is electrically connected to the first terminal of an i-th switch circuit and a first electrode of an (i+1)th capacitor (i is an integer of 1 to (p−1)),
wherein a second electrode of the p-th capacitor is electrically connected to the first terminal of the p-th switch circuit,
wherein an output terminal of the buffer circuit is electrically connected to the second terminal of each of the first to p-th switch circuits, and
wherein the third terminal of each of the first to p-th switch circuits is electrically connected to the first wiring supplying a low-level potential.
2. The semiconductor device according to claim 1 ,
wherein the memory cell is above the buffer circuit, the first switch, the second switch, and the third switch.
3. The semiconductor device according to claim 1 ,
wherein the memory cell includes a first transistor, and
wherein a channel formation region of the first transistor includes an oxide semiconductor.
4. The semiconductor device according to claim 1 ,
wherein each of the first switch, the second switch, and the third switch includes a second transistor, and
wherein a channel formation region of the second transistor includes silicon.
5. The semiconductor device according to claim 1 ,
wherein each of the first switch, the second switch, and the third switch includes a second transistor, and
wherein a channel formation region of the second transistor includes an oxide semiconductor.
6. The semiconductor device according to claim 1 ,
wherein the memory cell includes a first transistor,
wherein each of the first switch, the second switch, and the third switch includes a second transistor, and
wherein a channel formation region of each of the first transistor and the second transistor includes silicon.
7. The semiconductor device according to claim 1 ,
wherein the circuit comprises a (p+1)th capacitor, and
wherein the input terminal of the buffer circuit is electrically connected to a first electrode of the (p+1)th capacitor.
8. The semiconductor device according to claim 7 ,
wherein the (p+1)th capacitor is above the first switch, the second switch, and the third switch.
9. The semiconductor device according to claim 1 ,
wherein the memory cell includes a storage capacitor, and
wherein the first to p-th capacitors and the storage capacitor are above the first switch, the second switch, and the third switch.
10. An electronic component comprising:
the semiconductor device according to claim 1 , and
a processor core.
11. A semiconductor device comprising:
a memory cell;
a circuit; and
a first wiring,
wherein the circuit comprises a buffer circuit, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a second capacitor,
wherein a first terminal is electrically connected to a second terminal through the second switch,
wherein the first terminal is electrically connected to a third terminal through the third switch,
wherein a fourth terminal is electrically connected to a fifth terminal through the fourth switch,
wherein the fourth terminal is electrically connected to a sixth terminal through the fifth switch,
wherein a first electrode of the first capacitor is electrically connected to the memory cell,
wherein an input terminal of the buffer circuit is electrically connected to the memory cell through the first switch,
wherein a second electrode of the first capacitor is electrically connected to the first terminal and a first electrode of the second capacitor,
wherein a second electrode of the second capacitor is electrically connected to the fourth terminal,
wherein an output terminal of the buffer circuit is electrically connected to the second terminal and the fifth terminal, and
wherein each of the third terminal and the sixth terminal is electrically connected to the first wiring supplying a low-level potential.
12. The semiconductor device according to claim 11 ,
wherein the memory cell is above the buffer circuit, the first switch, the second switch, and the third switch.
13. The semiconductor device according to claim 11 ,
wherein the memory cell includes a first transistor, and
wherein a channel formation region of the first transistor includes an oxide semiconductor.
14. The semiconductor device according to claim 11 ,
wherein each of the first switch, the second switch, the third switch, the fourth switch, and the fifth switch includes a second transistor, and
wherein a channel formation region of the second transistor includes silicon.
15. The semiconductor device according to claim 11 ,
wherein each of the first switch, the second switch, the third switch, the fourth switch, and the fifth switch includes a second transistor, and
wherein a channel formation region of the second transistor includes an oxide semiconductor.
16. The semiconductor device according to claim 11 ,
wherein the memory cell includes a first transistor,
wherein each of the first switch, the second switch, the third switch, the fourth switch, and the fifth switch includes a second transistor, and
wherein a channel formation region of each of the first transistor and the second transistor includes silicon.
17. The semiconductor device according to claim 11 ,
wherein the circuit comprises a third capacitor, and
wherein the input terminal of the buffer circuit is electrically connected to a first electrode of the third capacitor.
18. The semiconductor device according to claim 17 ,
wherein the third capacitor is above the first switch, the second switch, and the third switch.
19. The semiconductor device according to claim 11 ,
wherein the memory cell includes a storage capacitor, and
wherein the first capacitor, the second capacitor, and the storage capacitor are above the first switch, the second switch, and the third switch.
20. An electronic component comprising:
the semiconductor device according to claim 11 , and
a processor core.