IP Library › Granted Patent US 10,186,575
Granted Patent B2
US 10,186,575 · App. 15/903,181 · Granted Jan 22, 2019

Silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device

Inventors: Yasuyuki Kawada (Tsukuba, JP); Shiyang Ji (Tsukuba, JP); Ryoji Kosugi (Tsukuba, JP); Hidenori Koketsu (Tokyo, JP); Kazuhiro Mochizuki (Tsukuba, JP)
Assignees: FUJI ELECTRIC CO., LTD.; MITSUBISHI ELECTRIC CORPORATION
H01L29/0634H01L21/046H01L21/0475H01L29/1095H01L29/1608H01L29/66068H01L29/66348H01L29/66621H01L29/66734H01L29/7811H01L29/7813H01L29/7825H01L29/7827H01L29/4236H01L29/7802
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Quick Facts
Patent No.
US 10,186,575
App. No.
15/903,181
Granted
Jan 22, 2019
Kind
B2
Abstract

In a silicon carbide semiconductor device, an n-type drift layer is formed on a front surface of an n ++ -type semiconductor substrate. Next, a trench is formed in the n-type drift layer, from a surface of the n-type drift layer. Next, a p-type pillar region is formed in the trench. A depth of the trench is at least three times a width of the trench. The p-type pillar region is formed by concurrently introducing a p-type first dopant and a gas containing an n-type second dopant incorporated at an atom position different from that of the first dopant.

Claims (20)

1. A silicon carbide semiconductor device comprising

a silicon carbide semiconductor substrate of a first conductivity type, having a front surface; and

a parallel pn layer having:

a first semiconductor layer of the first conductivity type provided on the front surface of the silicon carbide semiconductor substrate; and

a first semiconductor region of a second conductivity type embedded in a trench that is provided in the first semiconductor layer, from a surface of the first semiconductor layer, wherein

a depth of the trench is at least three times a width of the trench, and

the first semiconductor region contains

a first dopant of the second conductivity type determining a conductivity type of the first semiconductor region, and

a second dopant of the first conductivity incorporated at an atom position different from that of the first dopant, a carrier concentration of the first semiconductor region being uniform.

2. The silicon carbide semiconductor device according to claim 1 , wherein the carrier concentration of the first semiconductor region is in a range of 1×10 15 /cm 3 to 5×10 17 /cm 3 .

3. A method of manufacturing a silicon carbide semiconductor device, the method comprising:

forming a first semiconductor layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate of the first conductivity type;

forming a trench in the first semiconductor layer, from a surface of the first semiconductor layer, the trench having a depth at least three times a width of the trench; and

forming a first semiconductor region of a second conductivity type in the trench,

by introducing a first dopant of the second conductivity type and a gas containing a second dopant of the first conductivity type that is incorporated at an atom position different from that of the first dopant.

4. The method according to claim 3 , wherein forming a first semiconductor region further includes

depositing a portion of the first semiconductor region with introducing with the first dopant and without the second dopant until a thickness of the portion of the first semiconductor region at a side wall of the trench becomes 0.2 μm, and

after the thickness of the portion of the first semiconductor region becomes 0.2 μm, forming the rest of the first semiconductor region by introducing the first dopant and the second dopant.

5. The method according to claim 4 , wherein forming the rest of the first semiconductor region includes gradually increasing a flowrate of the gas containing the second dopant from a start of supplying the second dopant until formation of the first semiconductor region is complete.

6. The method according to claim 4 , wherein forming the rest of the first semiconductor region includes supplying the second dopant having an amount to be less than an amount of the first dopant, thereby forming the first semiconductor region having a carrier concentration of the first semiconductor region being in a range of 1×10 15 /cm 3 to 5×10 17 /cm 3 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2018
From: KAWADA, YASUYUKI; JI, SHIYANG; KOSUGI, RYOJI; KOKETSU, HIDENORI; MOCHIZUKI, KAZUHIRO
To: FUJI ELECTRIC CO., LTD.; MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 045754/0324 →
Priority Claims (1)
JP 2017-037763 · Feb 28, 2017 · national
Continuity (1)
Related Publication 20180248002A1 · Aug 30, 2018