System and method for voltage regulator self-burn-in test
The present disclosure provides a system and method enabling a self-burn-in test for a power supply device (PSD) of a server system using a multi-phase scheme. The PSD comprises a power-width modulation (PWM) controller, and a plurality of power stages. Each of the plurality of power stages comprises a driver, a high-side MOSFET, and a low-side MOSFET. In one aspect of the present disclosure, upon receiving a test mode command from a controller of the server system, the PWM controller can send a PWM signal to switch a specific power stage to the On state, and send at least another PWM signal that switches other power stage(s) of the plurality of power stages to the Tri-state. During a subsequent self-burn-in test of the specific power stage, low-side MOSFET(s) of the other power stage(s) can function as a load for the specific power stage.
1. A computer-implemented method for enabling a self-burn-in test of a power supply device (PSD) that comprises a modulation controller and a plurality of power stages, comprising:
sending a first signal to switch a specific power stage of the plurality of power stages to an On state;
sending at least one second signal to switch other power stage(s) of the plurality of power stages to a Tri-state, wherein the other power stage(s) functions as a load during a time period that the specific power stage is in the On state; and
collecting output voltage, output current and temperature data from the specific power stage.
2. The computer-implemented method of claim 1 , wherein each of the plurality of power stages comprises a driver, a high-side metal-oxide semiconductor field-effect transistor (MOSFET) and a low-side MOSFET, and wherein corresponding low-side MOSFET(s) of the other power stage(s) functions as the load during the time period that the specific power stage is in the On state.
3. The computer-implemented method of claim 1 , wherein each of the plurality of power stages comprises a voltage sensing circuit, a current sensing circuit and a temperature sensor.
4. The computer-implemented method of claim 3 , wherein collecting the output voltage, the output current and the temperature data comprises collecting the data from the voltage sensing circuit, the current sensing circuit, and the temperature sensor of the specific power stage.
5. The computer-implemented method of claim 4 , furthering comprising:
determining that the data fails a predetermined criterion; and
generating a warning signal indicating that the PSD has failed the self-burn-in test.
6. The computer-implemented method of claim 5 , wherein the predetermined criterion includes an output voltage range, an output current range, and a temperature range of the specific power stage.
7. The computer-implemented method of claim 4 , furthering comprising:
determining that the data has passed the predetermined criterion;
determining that at least one additional power stage of the PSD is still to be tested;
sending a third signal to switch one of the at least one additional power stage to the On state; and
sending at least one fourth signal to switch remaining power stage(s) of the plurality of power stages to the Tri-state.
8. The computer-implemented method of claim 1 , furthering comprising:
receiving a test mode command from a baseboard management controller (BMC) via system management bus (SMBus), inter-integrated circuit (I 2 C) bus, or power management bus (PMBus).
9. A system for enabling a self-burn-in test of a power supply device (PSD) that comprises a modulation controller and a plurality of power stages, comprising:
a processor; and
a computer-readable medium storing instructions that, when executed by the processor, cause the system to perform operations comprising:
sending a first signal to switch a specific power stage of the plurality of power stages to an On state;
sending at least one second signal to switch other power stage(s) of the plurality of power stages to a Tri-state, wherein the other power stage(s) functions as a load during a time period that the specific power stage is in the On state; and
collecting output voltage, output current and temperature data from the specific power stage.
10. The system of claim 9 , wherein each of the plurality of power stages comprises a driver, a high-side metal-oxide semiconductor field-effect transistor (MOSFET) and a low-side MOSFET, and wherein corresponding low-side MOSFET(s) of the other power stage(s) functions as the load during the time period that the specific power stage is in the On state.
11. The system of claim 9 , wherein each of the plurality of power stages comprises a voltage sensing circuit, a current sensing circuit and a temperature sensor.
12. The system of claim 11 , wherein collecting the output voltage, the output current and the temperature data comprises collecting the data from the voltage sensing circuit, the current sensing circuit, and the temperature sensor of the specific power stage.
13. The system of claim 12 , wherein the instructions, when executed by the processor, cause the system to perform operations comprising:
determining that the data fails a predetermined criterion; and
generating a warning signal indicating that the PSD has failed the self-burn-in test.
14. The system of claim 13 , wherein the predetermined criterion includes an output voltage range, an output current range, and a temperature range of the specific power stage.
15. The system of claim 12 , wherein the instructions, when executed by the processor, cause the system to perform operations comprising:
determining that the data has passed the predetermined criterion;
determining that at least one additional power stage of the PSD is still to be tested;
sending a third signal to switch one of the at least one additional power stage to the On state; and
sending at least one fourth signal to switch remaining power stage(s) of the plurality of power stages to the Tri-state.
16. The system of claim 9 , wherein the instructions, when executed by the processor, cause the system to perform operations comprising:
receiving a test mode command from a baseboard management controller (BMC) of the system via SMBus, I 2 C bus, or PMBus.
17. A non-transitory computer-readable storage medium including instructions that, when executed by at least one processor of a system, cause the system to perform operations enabling a self-burn-in test of a power supply device (PSD) that comprises a modulation controller and a plurality of power stages, comprising:
sending a first signal to switch a specific power stage of the plurality of power stages to an On state;
sending at least one second signal to switch other power stage(s) of the plurality of power stages to a Tri-state, wherein the other power stage(s) functions as a load during a time period that the specific power stage is in the On state; and
collecting output voltage, output current and temperature data from the specific power stage.
18. The non-transitory computer-readable storage medium of claim 17 , wherein each of the plurality of power stages comprises a voltage sensing circuit, a current sensing circuit and a temperature sensor, and wherein collecting the output voltage, the output current and the temperature data comprises collecting the data from the voltage sensing circuit, the current sensing circuit, and the temperature sensor of the specific power stage.
19. The non-transitory computer-readable storage medium of claim 18 , wherein the instructions when executed further cause the system to perform operations comprising:
determining that the data fails a predetermined criterion; and
generating a warning signal indicating that the PSD has failed the self-burn-in test.
20. The non-transitory computer-readable storage medium of claim 18 , wherein the instructions when executed further cause the system to perform operations comprising:
determining that the data has passed the predetermined criterion;
determining that at least one additional power stage of the PSD is still to be tested;
sending a third signal to switch one of the at least one additional power stage to the On state; and
sending at least one fourth signal to switch remaining power stage(s) of the plurality of power stages to the Tri-state.