Optimized call-return and binary translation
In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native instruction set architecture. The processor also includes a binary translator to translate the region of code. The region formation engine is to perform aggressive region formation, which includes forming a region across a boundary of a return instruction. The translated region of code is to prevent a side entry into the translated region of code at a translated return target instruction included in the translated region of code. In more specific examples, performing aggressive region formation includes a region formation grow phase and a region formation cleanup phase. In the grow phase priority may be given to growing complete paths from a call target to a corresponding return. The region formation cleanup phase may comprise eliminating call targets that are not reachable.
1. A processor, comprising:
a region formation engine to perform aggressive region formation of a region of code for translation from a guest instruction set architecture code to a translated instruction set architecture code,
wherein the aggressive region formation comprises forming the region of code across a boundary of a return (RET) instruction; and
a binary translator to:
translate the region of code; and
prevent a side entry into the translated region of code at a translated return target (RET_TGT′) included in the translated region of code, wherein the RET_TGT′ is translated from a return target (RET_TGT) in the guest instruction set architecture code, and
wherein the side entry is prevented based on an indication mapped to an instruction pointer of the RET_TGT.
2. The processor of claim 1 , wherein performing aggressive region formation comprises two-phase region formation.
3. The processor of claim 2 , wherein two-phase region formation comprises a region formation grow phase.
4. The processor of claim 3 , wherein the grow phase comprises a depth-first algorithm, wherein priority is given to growing complete paths from a call target (CALL_TGT) to a corresponding return (RET) instruction.
5. The processor of claim 4 , wherein the depth-first algorithm grants priority to growing complete paths over frequently used code.
6. The processor of claim 2 , wherein the two-phase region formation comprises a region formation cleanup phase.
7. The processor of claim 6 , wherein region formation cleanup comprises eliminating call targets (CALL_TGTs) that are not reachable.
8. The processor of claim 6 , wherein region formation cleanup comprises determining that there are multiple CALL_TGT to return target (RET_TGT) paths, determining that the region exceeds a heuristic size criterion, and eliminating less frequently used paths from the region.
9. The processor of claim 1 , wherein the processor further comprises a dual return stack buffer (DRSB), the DRSB comprising a RET_TGT field, a translated RET_TGT PRIME (RET_TGT′) field, a VALID field, and a LOCAL field to store the indication, wherein the RET_TGT′ field contains a RET_TGT′ instruction pointer corresponding to the translated RET_TGT.
10. The processor of claim 9 , wherein the processor is to provide a PUSH_DRSB_LOCAL instruction, wherein the PUSH_DRSB_LOCAL instruction pushes an entry onto the DRSB and sets the LOCAL field.
11. The processor of claim 9 , wherein the processor is to provide a PUSH_DRSB_LOCAL_FI instruction for fully inlined translations, wherein the PUSH_DRSB_LOCAL_FI instruction pushes an entry onto the DRSB and sets the LOCAL field.
12. The processor of claim 9 , wherein the processor is to provide a POP_DRSB_LOCAL instruction, wherein the POP_DRSB_LOCAL instruction pops an entry from the DRSB and, in response to determining that the LOCAL bit is set, passes control according to the RET_TGT′ instruction pointer.
13. The processor of claim 9 , wherein the processor is to provide a POP_DRSB_LOCAL instruction, wherein the POP_DRSB_LOCAL instruction pops an entry from the DRSB and, in response to determining that the LOCAL bit is not set, raises an error condition.
14. A system on a chip (SoC) configured for dynamic binary translation (DBT), comprising:
a memory;
one or more cores communicatively coupled to the memory;
auxiliary circuitry providing auxiliary functions to the one or more cores,
wherein the one or more cores comprise a processor block, comprising:
a region formation engine to perform aggressive region formation for a region of code to be translated from a guest instruction set architecture code to a translated instruction set architecture code, wherein the aggressive region formation comprises forming the region of code across a boundary of a return (RET) instruction; and
a binary translator to:
translate the region of code; and
prevent a side entry into the translated region of code at a translated return target (RET_TGT′) included in the translated region of code,
wherein the RET_TGT′ is translated from a return target (RET_TGT) in the guest instruction set architecture code, and wherein the side entry is prevented by mapping an indication to an instruction pointer of the RET_TGT.
15. The SoC of claim 14 , wherein performing aggressive region formation comprises two-phase region formation, and wherein the two-phase region formation comprises a region formation grow phase.
16. The SoC of claim 15 , wherein the grow phase comprises a depth-first algorithm, wherein priority is given to growing complete paths from a call target (CALL_TGT) to a corresponding return (RET) instruction, and the depth-first algorithm grants priority to growing complete paths over frequently used code.
17. The SoC of claim 16 , wherein performing aggressive region formation comprises two-phase region formation, and wherein the two-phase region formation comprises a region formation cleanup phase.
18. The SoC of claim 17 , wherein region formation cleanup comprises eliminating CALL_TGTs that are not reachable, and wherein the region formation cleanup comprises determining that there are multiple CALL_TGT to return target (RET_TGT) paths, determining that the region exceeds a heuristic size criterion, and eliminating less frequently used paths from the region.
19. The SoC of any of claim 15 , wherein the SoC further comprises a dual return stack buffer (DRSB), the DRSB comprising a RET_TGT field, a translated RET_TGT PRIME (RET_TGT′) field, a VALID field, and a LOCAL field to store the indication, wherein the RET_TGT′ field contains a RET_TGT′ instruction pointer corresponding to the translated RET_TGT.
20. The SoC of claim 19 , wherein the SoC is to provide a PUSH_DRSB_LOCAL instruction, wherein the PUSH_DRSB_LOCAL instruction pushes an entry onto the DRSB and sets the LOCAL field.
21. The SoC of claim 19 , wherein the SoC is to provide a PUSH_DRSB_LOCAL_FI instruction for fully inlined translations, wherein the PUSH_DRSB_LOCAL_FI instruction pushes an entry onto the DRSB and sets the LOCAL field.
22. The SoC of claim 19 , wherein the SoC is to provide a POP_DRSB_LOCAL instruction, wherein the POP_DRSB_LOCAL instruction pops an entry from the DRSB and, in response to determining that the LOCAL bit is set, passes control according to the RET_TGT′ instruction pointer.
23. A method of providing dynamic binary translation for a processor, comprising:
performing region formation comprising identifying a region of code for translation from a guest instruction set architecture code to a translated instruction set architecture code, comprising aggressive region formation comprising:
forming the region of code across a boundary of a return (RET) instruction;
performing binary translation to translate the region of code; and
preventing a side entry into the translated region of code at a translated return target (RET_TGT′) included in the translated region of code,
wherein the RET_TGT′ is translated from a return target (RET_TGT) in the guest instruction set architecture code, and wherein the side entry is prevented based on an indication mapped to an instruction pointer of the RET_TGT.
24. The method of claim 23 , wherein aggressive region formation comprises a region formation grow phase, and a region formation cleanup phase.
25. The method of claim 24 , further comprising accessing a dual return stack buffer (DRSB) register comprising a LOCAL field.